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  • Research Article
  • Open Access

High-Speed Smart Camera with High Resolution

EURASIP Journal on Embedded Systems20072007:024163

  • Received: 1 May 2006
  • Accepted: 10 December 2006
  • Published:


High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs, readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded processing. Two types of algorithms have been implemented. A compression algorithm, specific to high-speed imaging constraints, has been implemented. This implementation allows to reduce the large data flow (6.55 Gbps) and to propose a transfer on a serial output link (USB 2.0). The second type of algorithm is dedicated to feature extraction such as edge detection, markers extraction, or image analysis, wavelet analysis, and object tracking. These image processing algorithms have been implemented into an FPGA embedded inside the camera. These implementations are low-cost in terms of hardware resources. This FPGA technology allows us to process in real time 500 images per second with a 1280×1024 resolution. This camera system is a reconfigurable platform, other image processing algorithms can be implemented.


  • Feature Extraction
  • Object Tracking
  • Compression Algorithm
  • Hardware Resource
  • Image Processing Algorithm

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Authors’ Affiliations

Laboratoire Le2i, UMR CNRS 5158, Université de Bourgogne, Aile des Sciences de l'Ingenieur, BP 47870, Dijon, Cedex 21078, France


  1. Thorpe S, Fize D, Marlot C: Speed of processing in the human visual system. Nature 1996,381(6582):520-522. 10.1038/381520a0View ArticleGoogle Scholar
  2. Kondo Y, Maruno H, Tominaga H, Soya H, Etoh TG: An ultrahigh-speed video camera and its applications. 25th International Congress on High-Speed Photography and Photonics, September-October 2002, Beaune, France, Proceedings of SPIE 4948: 53-58.View ArticleGoogle Scholar
  3. Tajima K, Tamura K, Awano K: Design of 1-M pixels high-speed video camera. 25th International Congress on High-Speed Photography and Photonics, September-October 2002, Beaune, France, Proceedings of SPIE 4948: 83-88.View ArticleGoogle Scholar
  4. Wolf W, Ozer B, Lv T: Smart cameras as embedded systems. Computer 2002,35(9):48-53. 10.1109/MC.2002.1033027View ArticleGoogle Scholar
  5. Fauvet E, Paindavoine M, Cannard F: Human movement analysis with image processing in real time. 19th International Congress on High-Speed Photography and Photonics, September 1991, Cambridge, UK, Proceedings of SPIE 1358: 620-630.View ArticleGoogle Scholar
  6. Bouffault F, Febvre J, Milan C, Paindavoine M, Grapin JC: A high-speed video microsystem. Measurement Science and Technology 1997,8(4):398-402. 10.1088/0957-0233/8/4/006View ArticleGoogle Scholar
  7. Bouffault F, Milan C, Paindavoine M, Febvre J: High-speed cameras using a CCD image sensor and a new high-speed image sensor for biological applications. 21st International Congress on: High-Speed Photography and Photonics, August-September 1994, Taejon, Korea, Proceedings of SPIE 2513: 252-258.Google Scholar
  8. Paindavoine M, Dolard D, Grapin J-C: Real-time imaging system applied to human movement analysis. Advanced Signal Processing Algorithms, Architectures, and Implementations IX, July 1999, Denver, Colo, USA, Proceedings of SPIE 3807: 150-156.View ArticleGoogle Scholar
  9. Xilinx
  10. Nac : Memrecam fx K4 High-Speed Color Video System.
  11. Photron : Ultima APX-RS Fastcam.
  12. Weinberger
  13. Micron
  14. Fossum ER: Active pixel sensors: are CCDs dinosaurs? Charge-Coupled Devices and Solid State Optical Sensors III, February 1993, San Jose, Calif, USA, Proceedings of SPIE 1900: 2-14.View ArticleGoogle Scholar
  15. Litwiller D: CCD vs. CMOS: facts and fiction. Photonics Spectra 2001,35(1):154-158.Google Scholar
  16. USB2.0
  17. Huffman DA: A method for construction of minimum-redundancy codes. Proceedings of IRE 1952,40(9):1098-1101. 10.1109/JRPROC.1952.273898View ArticleGoogle Scholar
  18. Ziv J, Lempel A: A universal algorithm for sequential data compression. IEEE Transactions on Information Theory 1977,23(3):337-343. 10.1109/TIT.1977.1055714MATHMathSciNetView ArticleGoogle Scholar
  19. Pennebaker WB, Mitchell JL: JPEG Still Image Data Compression Standard. Kluwer Academic, Norwell, Mass, USA; 1992.Google Scholar
  20. JPEG Commitee
  21. Taubman DS, Marcellin MW: JPEG 2000: Image Compression Fundamentals, Standards and Practice. Kluwer Academic, Norwell, Mass, USA; 2001.Google Scholar
  22. Mallat SG: A theory for multiresolution signal decomposition: the wavelet representation. IEEE Transactions on Pattern Analysis and Machine Intelligence 1989,11(7):674-693. 10.1109/34.192463MATHView ArticleGoogle Scholar
  23. Taubman D: High performance scalable image compression with EBCOT. IEEE Transactions on Image Processing 2000,9(7):1158-1170. 10.1109/83.847830View ArticleGoogle Scholar
  24. Pereira FC, Ebrahimi T: The MPEG-4 Book. Prentice-Hall PTR, Upper Saddle River, NJ, USA; 2002.Google Scholar
  25. MPEG Commitee
  26. Santa-Cruz D, Ebrahimi T, Askelof J, Larsson M, Christopoulos CA: JPEG 2000 still image coding versus other standards. Applications of Digital Image Processing XXIII, July 2000, San Diego, Calif, USA, Proceedings of SPIE 4115: 446-454.View ArticleGoogle Scholar
  28. Schumacher P, Paluszkiewicz M, Ballantyne R, Turney R: An efficient JPEG2000 encoder implemented on a platform FPGA. Applications of Digital Image Processing XXVI, August 2003, San Diego, Calif, USA, Proceedings of SPIE 5203: 306-313.View ArticleGoogle Scholar
  29. Schumacher P, Chung W: FPGA-based MPEG-4 codec. DSP Magazine 2005, 8-9.Google Scholar
  30. Dubois J, Mattavelli M, Pierrefeu L, Miteran J: Configurable motion-estimation hardware accelerator module for the MPEG-4 reference hardware description platform. Proceedings of IEEE International Conference on Image Processing (ICIP '05), September 2005, Genova, Italy 3: 1040-1043.Google Scholar
  31. Alam M, Badawy W, Jullien G: A new time distributed DCT architecture for MPEG-4 hardware reference model. IEEE Transactions on Circuits and Systems for Video Technology 2005,15(5):726-730. 10.1109/TCSVT.2005.846429View ArticleGoogle Scholar
  32. Chiang T, Mattavelli M, Turney RD: Introduction to the special issue on integrated multimedia platforms. IEEE Transactions on Circuits and Systems for Video Technology 2005,15(5):589-592. 10.1109/TCSVT.2005.846889View ArticleGoogle Scholar
  33. Staller A, Dillinger P, Männer R: Implementation of the JPEG 2000 standard on a virtex 1000 FPGA. Proceedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL '02), September 2002, Montpellier, France 503-512.Google Scholar
  34. Grossmann A, Morlet J: Decomposition of hardy functions into square integrable wavelets of constant shape. SIAM Journal on Mathematical Analysis 1984,15(4):723-736. 10.1137/0515056MATHMathSciNetView ArticleGoogle Scholar
  35. Sweldens W: Lifting scheme: a new philosophy in biorthogonal wavelet constructions. Wavelet Applications in Signal and Image Processing III, July 1995, San Diego, Calif, USA, Proceedings of SPIE 2569: 68-79.View ArticleGoogle Scholar
  36. Cohen A, Daubechies I, Feauveau J-C: Biorthogonal bases of compactly supported wavelets. Communications on Pure and Applied Mathematics 1992,45(5):485-560. 10.1002/cpa.3160450502MATHMathSciNetView ArticleGoogle Scholar
  37. Diou C, Torres L, Robert M: Implementation of a wavelet transform architecture for image processing. Proceedings of the 10th International Conference on Very Large Scale Integration (VLSI '99), December 1999, Lisbon, Portugal 101-112.Google Scholar
  38. Trier OD, Jain AK: Goal-directed evaluation of binarization methods. IEEE Transactions on Pattern Analysis and Machine Intelligence 1995,17(12):1191-1201. 10.1109/34.476511View ArticleGoogle Scholar
  39. Dubois J, Mattavelli M: Embedded co-processor architecture for CMOS based image acquisition. Proceedings of IEEE International Conference on Image Processing (ICIP '03), September 2003, Barcelona, Spain 2: 591-594.Google Scholar
  40. Ribotta MG, Provencher J, Feraboli-Lohnherr D, Rossignol S, Privat A, Orsal D: Activation of locomotion in adult chronic spinal rats is achieved by transplantation of embryonic raphe cells reinnervating a precise lumbar level. Journal of Neuroscience 2000,20(13):5144-5152.Google Scholar
  41. Rivero D, Paindavoine M, Petit S: Real-time sub-pixel cross bar position metrology. Real-Time Imaging 2002,8(2):105-113. 10.1006/rtim.2001.0259MATHView ArticleGoogle Scholar
  42. Bourennane E, Gouton P, Paindavoine M, Truchetet F: Generalization of Canny-Deriche filter for detection of noisy exponential edge. Signal Processing 2002,82(10):1317-1328. 10.1016/S0165-1684(02)00283-9MATHView ArticleGoogle Scholar
  43. Pirson A, Jacquot J-L, Court T, David D: A highly efficient method for synthesizing some digital filters. Proceedings of European Signal Processing Conference (EUSIPCO '88), September 1988, Grenoble, France Google Scholar
  44. Berry F, Chalimbaud P: Smart camera and active vision: the active detector formalism. Electronic Imaging 2004,14(1):2-9.Google Scholar
  45. Muehlmann U, Ribo M, Lang P, Pinz A: A new high speed CMOS camera for real-time tracking applications. Proceedings of IEEE International Conference on Robotics and Automation (ICRA '04), April-May 2004, New Orleans, La, USA 5: 5195-5200.Google Scholar
  46. Lepistö N, Thörnberg B, O'Nils M: High-performance FPGA based camera architecture for range imaging. Proceedings of the 23rd NORCHIP Conference, November 2005, Oulu, Finland 165-168.Google Scholar
  47. Caarls W, Jonker P, Corporaal H: Smartcam: devices for embedded intelligent cameras. Proceedings of the 3rd PROGRESS Workshop on Embedded Systems, October 2002, Utrecht, The Netherlands 1-4.Google Scholar
  48. Yang F, Paindavoine M: Implementation of an RBF neural network on embedded systems: real-time face tracking and identity verification. IEEE Transactions on Neural Networks 2003,14(5):1162-1175. 10.1109/TNN.2003.816035View ArticleGoogle Scholar


© R. Mosqueron et al. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.