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  • Research Article
  • Open Access

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

EURASIP Journal on Embedded Systems20062006:081309

  • Received: 15 December 2005
  • Accepted: 2 June 2006
  • Published:


Field-programmable gate arrays (FPGAs) are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs), through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs). In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.


  • Digital Signal Processor
  • Operational Flexibility
  • Algorithm Parallelism
  • Error Rate Performance
  • Wireless Channel Statistic

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Authors’ Affiliations

Department of Electrical and Computer Engineering, Queen's University, Kingston, ON, K7L 3N6, Canada
Communications Signal Processing Laboratory, Department of Electrical and Computer Engineering, Hanyang University, Seoul, Korea
CMC Microsystems, Kingston, ON, K7L 3N6, Canada


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© Constantin Siriteanu et al. 2006

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.