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FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems
EURASIP Journal on Embedded Systems volume 2006, Article number: 081309 (2006)
Field-programmable gate arrays (FPGAs) are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs), through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs). In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.
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Siriteanu, C., Blostein, S.D. & Millar, J. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems. J Embedded Systems 2006, 081309 (2006). https://doi.org/10.1155/ES/2006/81309
- Digital Signal Processor
- Operational Flexibility
- Algorithm Parallelism
- Error Rate Performance
- Wireless Channel Statistic