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A Visual Environment for Real-Time Image Processing in Hardware (VERTIPH)

EURASIP Journal on Embedded Systems volume 2006, Article number: 072962 (2006) Cite this article

Abstract

Real-time video processing is an image-processing application that is ideally suited to implementation on FPGAs. We discuss the strengths and weaknesses of a number of existing languages and hardware compilers that have been developed for specifying image processing algorithms on FPGAs. We propose VERTIPH, a new multiple-view visual language that avoids the weaknesses we identify. A VERTIPH design incorporates three different views, each tailored to a different aspect of the image processing system under development; an overall architectural view, a computational view, and a resource and scheduling view.

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Authors and Affiliations

  1. Institute of Information Sciences and Technology, Massey University, Private Bag 11222, Palmerston North, 4442, New Zealand

    CT Johnston, DG Bailey & P Lyons

Authors
  1. CT Johnston
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  2. DG Bailey
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  3. P Lyons
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Correspondence to CT Johnston.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Johnston, C., Bailey, D. & Lyons, P. A Visual Environment for Real-Time Image Processing in Hardware (VERTIPH). J Embedded Systems 2006, 072962 (2006). https://doi.org/10.1155/ES/2006/72962

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  • DOI: https://doi.org/10.1155/ES/2006/72962

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