- Research Article
- Open Access
Signal Processing with Teams of Embedded Workhorse Processors
EURASIP Journal on Embedded Systemsvolume 2006, Article number: 069484 (2006)
Advanced signal processing for voice and data in wired or wireless environments can require massive computational power. Due to the complexity and continuing evolution of such systems, it is desirable to maintain as much software controllability in the field as possible. Time to market can also be improved by reducing the amount of hardware design. This paper describes an architecture based on clusters of embedded "workhorse" processors which can be dynamically harnessed in real time to support a wide range of computational tasks. Low-power processors and memory are important ingredients in such a highly parallel environment.
Holma H, Toskala A (Eds): WCDMA for UMTS. 2nd edition. John Wiley & Sons, New York, NY, USA; 2002.
Digital cellular telecommunications system (Phase 2+); Adaptive Multi-Rate (AMR); Speech processing functions; General description GSM 06.71 version 7.0.2 Release 1998
Dual rate speech coder for multimedia communications transmitting at 5.3 and 6.3 kbit/s ITUT Recommendation 7.723.1 (03/96)
Coding of Speech at 8 kbit/s using Conjugate-Structure Algebraic-Code-Excited Linear-Prediction (CS-ACELP) ITUT Recommendation G.729 (03/96)
Karimi HR, Anderson NW: Novel and efficient solution to block-based joint-detection using approximate Cholesky factorization. Proceedings of the 9th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC '98), September 1998, Boston, Mass, USA 3: 1340-1345.
Hobson RF, Wong PS: A parallel embedded-processor architecture for ATM reassembly. IEEE/ACM Transactions on Networking 1999,7(1):23-37. 10.1109/90.759314
Ching TCP: Custom hardware implementation for a conjugate-structure algebraic-code- excited linear prediction (CS-ACELP) voice coding algorithm, M.Eng.thesis. Simon Fraser, University, Burnaby, BC, Canada; 2000.
Bindra A: Novel architectures pack multiple DSP cores on-chip (parts 1 and 2). Electronic Design 2001.
Bateman A: State-of-the-art DSP's. Global DSP 2005.,2(4, 11 pages):
Nickolls J, Madar LJ III, Johnson S, Rustagi V, Unger K, Choudhury M: Calisto: a low-power single-chip multiprocessor communications platform. IEEE Micro 2003,23(2):29-43. 10.1109/MM.2003.1196113
Kozyrakis CE, Patterson DA: Scalable vector processors for embedded systems. IEEE Micro 2003,23(6):36-45. 10.1109/MM.2003.1261385
Texas Instruments : TNETV3010 Infrastructure VOP Gateway Solution. Product Bulletin SPAT141, 2003
Intrinsity Inc : 3G Baseband Chip-Rate Processing Using the Intrinsity FastMATH Pocessor. White Paper version 1.6, 2003
Intrinsity Inc : RACH Preamble Detection. White Paper version 1.0, 2003
Foodeei M: The system-on-a-chip approach to VoIP systems yields countless benefits for service providers. Centillium Communications Inc
Centillium Com. Inc : Entropia III CT-GWC4672. Data Sheet, October 2003, version 1.1
Fuller P: A practical approach to parallel processing for Wireless DSP. picoChip Designs Ltd., March 2004
picoChip Designs Ltd : RACH Preamble Detection and Multipath Searching using the FAU. Application Note, July 2004
Hobson RF, Ressl B, Dyck AR: Processor cluster architecture and associated parallel processing methods. US patent 6,959,372, 2005; "Hierarchical bus structure and memory access protocol for systems," US patent 7,085,866, 2006
Tom M: Design and implementation of a global memory controller unit for a voice over packet signal processor, B.A.Sc. thesis. Simon Fraser University, Burnaby, BC, Canada; 2002.
Wightman R: Design of a DSP unit for a voice over packet processor, B.A.Sc. thesis. Simon Fraser University, Burnaby, BC, Canada; 2002.
Chen G: High performance DSP attachment on SOC for VOIP application, M.A.Sc. thesis. Simon Fraser University, Burnaby, BC, Canada; 2001.
Hennessy JL, Patterson DA: Computer Organization and Design. Morgan Kaufmann, San Francisco, Calif, USA; 1998.
Hobson RF, Dyck AR, Cheung KL: SoC features for a multi-processor WCDMA base-station modem. Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, July 2004, Banff, Alberta, Canada 318-321.
Ngun R: Design of a task control unit for a voice-over-packet codec, B.A.Sc. thesis. Simon Fraser University, Burnaby, BC, Canada; 2001.
Lehoczky J, Sha L, Ding Y: The rate monotonic scheduling algorithm: exact characterization and average case behavior. Proceedings of the IEEE Real-Time Systems Symposium, December 1989, Santa Monica, Calif, USA 166-171.
Gai P, Abeni L, Buttazzo G: Multiprocessor DSP scheduling in system-on-a-chip architectures. Proceedings of the 14th IEEE Euromicro Conference on Real-Time Systems, June 2002, Vienna, Austria 231-238.
Freescale Semiconductor Inc : Engineering the Multi-Channel Universal Port DSP Application: The Technology Behind the Surf Multi-Access Pool (SMP). http://www.freescale.com
Kaiway GA: Data transfer mechanism for a voice over packet parallel processing system, B.A.Sc. thesis. Simon Fraser University, Burnaby, BC, Canada; 2002.
Ressl B: Implementation of ITU G.729 for the PEPIII Processor, M.Eng. Thesis. Simon Fraser University, Burnaby, BC, Canada; 2001.
Proposal for RACH Preambles Motorola, Texas Instruments, TSG-RAN Working Group 1 Meeting #6, document 3GPP/TSGR1#6(99)893, July 1999
Hobson RF: A New Single-Ended SRAM Cell With Write-Assist. IEEE Transaction on VLSI Systems