Skip to main content


Efficient Design Methods for Embedded Communication Systems


Nowadays, design of embedded systems is confronted with complex signal processing algorithms and a multitude of computational intensive multimedia applications, while time to product launch has been extremely reduced. Especially in the wireless domain, those challenges are stacked with tough requirements on power consumption and chip size. Unfortunately, design productivity did not undergo a similar progression, and therefore fails to cope with the heterogeneity of modern architectures. Electronic design automation tools exhibit deep gaps in the design flow like high-level characterization of algorithms, floating-point to fixed-point conversion, hardware/software partitioning, and virtual prototyping. This tutorial paper surveys several promising approaches to solve the widespread design problems in this field. An overview over consistent design methodologies that establish a framework for connecting the different design tasks is given. This is followed by a discussion of solutions for the integrated automation of specific design tasks.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74]


  1. 1.

    Neuvo Y: Cellular phones as embedded systems. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '04), February 2004, San Francisco, Calif, USA 1: 32-37.

  2. 2.

    Hausner J, Denk R: Implementation of signal processing algorithms for 3G and beyond. IEEE Microwave and Wireless Components Letters 2003,13(8):302-304.

  3. 3.

    Subramanian R: Shannon vs. Moore: driving the evolution of signal processing platforms in wireless communications. Proceedings of IEEE Workshop on Signal Processing Systems (SIPS '02), October 2002, San Diego, Calif, USA 2.

  4. 4.

    Moore G: Cramming more components onto integrated circuits. Electronics Magazine 1965,38(8):114-117.

  5. 5.

    International SEMATECH : International Technology Roadmap for Semiconductors. 1999.

  6. 6.

    Rupp M, Burg A, Beck E: Rapid prototyping for wireless designs: the five-ones approach. Signal Processing 2003,83(7):1427-1444. 10.1016/S0165-1684(03)00090-2

  7. 7.

    Moigne RL, Pasquier O, Calvez J-P: A graphical tool for system-level modeling and simulation with systemC. Proceedings of the Forum on Specification & Design Languages (FDL '03), September 2003, Frankfurt, Germany

  8. 8.

    Karsai G, Sztipanovits J, Ledeczi A, Bapty T: Model-integrated development of embedded software. Proceedings of the IEEE 2003,91(1):145-164. 10.1109/JPROC.2002.805824

  9. 9.

    Karsai G: Design tool integration: an exercise in semantic interoperability. Proceedings of the 7th IEEE International Conference and Workshop on the Engineering of Computer Based Systems (ECBS '00), April 2000, Edinburgh, UK 272-278.

  10. 10.

    Synopsys Inc : Galaxy Design Platform.

  11. 11.

    SPIRIT Consortium

  12. 12.

    SPIRIT SchemaWorking Group Membership : SPIRIT-User Guide v1.1. SPIRIT Consortium, San Diego, Calif, USA; 2005.

  13. 13.

    Posadas H, Herrera F, Fernández V, Sánchez P, Villar E, Blasco F: Single source design environment for embedded systems based on SystemC. Design Automation for Embedded Systems 2004,9(4):293-312. 10.1007/s10617-005-1199-z

  14. 14.

    Raulet M, Urban F, Nezan J-F, Moy C, Deforges O, Sorel Y: Rapid prototyping for heterogeneous multicomponent systems: an MPEG-4 stream over a UMTS communication link. EURASIP Journal on Applied Signal Processing 2006, 2006: 1-13. special issue on design methods for DSP systems

  15. 15.

    Belanović P, Knerr B, Holzer M, Sauzon G, Rupp M: A consistent design methodology for wireless embedded systems. EURASIP Journal on Applied Signal Processing 2005,2005(16):2598-2612. special issue on DSP enabled radio 10.1155/ASP.2005.2598

  16. 16.

    MySQL Database Products

  17. 17.

    Knerr B, Belanović P, Holzer M, Sauzon G, Rupp M: Design flow improvements for embedded wireless receivers. Proceedings of the 12th European Signal Processing Conference (EUSIPCO '04), September 2004, Vienna, Austria 2015-2018.

  18. 18.

    Belanović P, Knerr B, Holzer M, Rupp M: A fully automated environment for verification of virtual prototypes. EURASIP Journal on Applied Signal Processing 2006., 2006: special issue on design methods for DSP systems

  19. 19.

    Knerr B, Holzer M, Rupp M: HW/SW partitioning using high level metrics. Proceedings of International Conference on Computer, Communication and Control Technologies (CCCT '04), August 2004, Austin, Tex, USA 8: 33-38.

  20. 20.

    Holzer M, Rupp M: Static code analysis of functional descriptions in systemC. Proceedings of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA '06), January 2006, Kuala Lumpur, Malaysia 243-248.

  21. 21.

    Belanović P, Rupp M: Automated floating-point to fixed-point conversion with the fixify environment. Proceedings of the 16th International Workshop on Rapid System Prototyping (RSP '05), June 2005, Montreal, Canada 172-178.

  22. 22.

    Sheppered M, Ince D: Derivation and Validation of Software Metrics. Oxford University Press, New York, NY, USA; 1993.

  23. 23.

    Boehm BW: Software Engineering Economics. Prentice-Hall, Englewood Cliffs, NJ, USA; 1981.

  24. 24.

    Moullec YL, Koch P, Diguet J-P, Philippe J-L: Design trotter: building and selecting architectures for embedded multimedia applications. Proceedings of IEEE International Symposium on Consumer Electronics (ISCE '03), December 2003, Sydney, Australia

  25. 25.

    McCabe T: A complexity measure. IEEE Transaction of Software Engineering 1976,2(4):308-320.

  26. 26.

    Poole J: A method to determine a basis set of paths to perform program testing. In Report 5737. U.S. Department of Commerce/National Institute of Standards and Technology, Gaithersburg, Md, USA; 1995.

  27. 27.

    Gajski D, Dutt N, Wu A, Lin S: High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic, Norwell, Mass, USA; 1992.

  28. 28.

    Pal Singh J, Kumar A, Kumar S: A multiplier generator for Xilinx FPGA's. Proceedings of the 9th IEEE International Conference on VLSI Design, January 1996, Bangalore, India 322-323.

  29. 29.

    Büyüksahin KM, Najm FN: High-level area estimation. Proceedings of International Symposium on Low Power Electronics and Design (ISLPED '02), August 2002, Monterey, Calif, USA 271-274.

  30. 30.

    Brandolese C, Fornaciari W, Salice F: An area estimation methodology for FPGA based designs at SystemC-level. Proceedings of the 41st Design Automation Conference (DAC '04), June 2004, San Diego, Calif, USA 129-132.

  31. 31.

    Holzer M, Rupp M: Static estimation of the execution time for hardware accelerators in system-on-chips. Proceedings of International Symposium on System-on-Chip (SoC '05), November 2005, Tampere, Finland 62-65.

  32. 32.

    Posadas H, Herrera F, Sánchez P, Villar E, Blasco F: System-level performance analysis in SystemC. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '04), February 2004, Paris, France 1: 378-383.

  33. 33.

    Bjureus P, Millberg M, Jantsch A: FPGA resource and timing estimation from Matlab execution traces. Proceedings of the 10th International Symposium on Workshop on Hardware/Software Codesign, May 2002, Estes Park, Colo, USA 31-36.

  34. 34.

    Devadas S, Malik S: A survey of optimization techniques targeting low power VLSI circuits. Proceedings of the 32nd ACM/IEEE Conference on Design Automation (DAC '95), June 1995, San Francisco, Calif, USA 242-247.

  35. 35.

    Fornaciari W, Gubian P, Sciuto D, Silvano C: Power estimation of embedded systems: a hardware/software codesign approach. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1998,6(2):266-275.

  36. 36.

    Landman P: High-level power estimation. Proceedings of International Symposium on Low Power Electronics and Design, August 1996, Monterey, Calif, USA 29-35.

  37. 37.

    Moon TK, Stirling WC: Mathematical Methods and Algorithms for Signal Processing. Prentice-Hall, Upper Saddle River, NJ, USA; 2000.

  38. 38.

    Sciuto D, Salice F, Pomante L, Fornaciari W: Metrics for design space exploration of heterogeneous multiprocessor embedded systems. Proceedings of International Workshop on Hardware/Software Codesign, May 2002, Estes Park, Colo, USA 55-60.

  39. 39.

    Keding H, Willems M, Coors M, Meyr H: FRIDGE: a fixed-point design and simulation environment. Proceedings of Design, Automation and Test In Europe (DATE '98), February 1998, Paris, France 429-435.

  40. 40.

    Synopsys : Converting ANSI-C into fixed-point using Cocentric fixed-point designer. Synopsys, Mountain View, Calif, USA; 2000.

  41. 41.

    Stephenson M, Babb J, Amarasinghe S: Bitwidth analysis with application to silicon compilation. Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '00), June 2000, Vancouver, BC, Canada 108-120.

  42. 42.

    Menard D, Chillet D, Charot F, Sentieys O: Automatic floating-point to fixed-point conversion for DSP code generation. Proceedings of International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES '02), October 2002, Grenoble, France 270-276.

  43. 43.

    Fang CF, Rutenbar RA, Chen T: Fast, accurate static analysis for fixed-point finite-precision effects in DSP designs. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2003, San Jose, Calif, USA 275-282.

  44. 44.

    Kim S, Kum K-I, Sung W: Fixed-point optimization utility for C and C++ based digital signal processing programs. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 1998,45(11):1455-1464. 10.1109/82.735357

  45. 45.

    Cao Y, Yasuura H: Quality-driven design by bitwidth optimization for video applications. Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, January 2003, Kitakyushu, Japan 532-537.

  46. 46.

    Shi C, Brodersen RW: An automated floating-point to fixed-point conversion methodology. Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP '03), April 2003, Hong Kong 2: 529-532.

  47. 47.

    MathWorks Simulink

  48. 48.

    Hromkovič J: Algorithmics for Hard Problems. 2nd edition. Springer, New York, NY, USA; 2003.

  49. 49.

    Mehlführer C, Kaltenberger F, Rupp M, Humer G: A scalable rapid prototyping system for real-time MIMO OFDM transmission. Proceedings of the 2nd IEE/EURASIP Conference on DSP Enabled Radio, September 2005, Southampton, UK

  50. 50.

    Ernst R, Henkel J, Benner T: Hardware-software cosynthesis for microcontrollers. IEEE Design & Test 1993,10(4):64-75. 10.1109/54.245964

  51. 51.

    Kirkpatrick S, Gelatt CD, Vecchi MP: Optimization by simulated annealing. Science 1983,220(4598):671-680. 10.1126/science.220.4598.671

  52. 52.

    Henkel D, Herrman J, Ernst R: An approach to the adaption of estimated cost parameters in the COSYMA system. Proceedings of the 3rd International Workshop on Hardware/Software Codesign (CODES '94), September 1994, Grenoble, France 100-107.

  53. 53.

    Henkel J, Ernst R: Hardware/software partitioner using a dynamically determined granularity. Proceedings of the 34th Annual Conference on Design Automation (DAC '97), June 1997, Anaheim, Calif, USA 691-696.

  54. 54.

    Kalavade A, Lee EA: Global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem. Proceedings of the 3rd International Workshop on Hardware/Software Codesign (CODES '94), September 1994, Grenoble, France 42-48.

  55. 55.

    Lee EA: Overview of the ptolemy project. University of Berkeley, Berkeley, Calif, USA; 2001.

  56. 56.

    Kernighan B, Lin S: An efficient heuristic procedure in partitioning graphs. Bell System Technical Journal 1970,49(2):291-307.

  57. 57.

    Kalavade A, Lee EA: Extended partitioning problem: hardware/software mapping and implementation-bin selection. Proceedings of the 6th IEEE International Workshop on Rapid System Prototyping, June 1995, Chapel Hill, NC, USA 12-18.

  58. 58.

    Eles P, Peng Z, Kuchcinski K, Doboli A: System level hardware/software partitioning based on simulated annealing and tabu search. Design Automation for Embedded Systems 1997,2(1):5-32. 10.1023/A:1008857008151

  59. 59.

    Vahid F, Le TD: Extending the kernighan/lin heuristic for hardware and software functional partitioning. Design Automation for Embedded Systems 1997,2(2):237-261. 10.1023/A:1008836303344

  60. 60.

    Chatha KS, Vemuri R: Iterative algorithm for hardware-software partitioning, hardware design space exploration and scheduling. Design Automation for Embedded Systems 2000,5(3):281-293. 10.1023/A:1008954218909

  61. 61.

    Chatha KS, Vemuri R: Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2002,10(3):193-208.

  62. 62.

    Wiangtong T, Cheung PYK, Luk W: Comparing three heuristic search methods for functional partitioning in hardware-software codesign. Design Automation for Embedded Systems 2002,6(4):425-449. 10.1023/A:1016567828852

  63. 63.

    Knerr B, Holzer M, Rupp M: Fast rescheduling of multi-rate systems for HW/SW partitioning algorithms. Proceedings of the 39th Annual Asilomar Conference on Signals, Systems, and Computers, October 2005, Monterey, Calif, USA

  64. 64.

    Knerr B, Holzer M, Rupp M: A fast rescheduling heuristic of SDF graphs for HW/SW partitioning algorithms. Proceedings of the 1st International Conference on Communication System Software and Middleware (COMSWARE '06), January 2006, New Delhi, India

  65. 65.

    Lee EA, Messerschmitt DG: Synchronous data flow. Proceedings of the IEEE 1987,75(9):1235-1245.

  66. 66.

    Hu TC: Parallel sequencing and assembly line problems. In Tech. Rep. 6. Operations Research Center, Cambridge, Mass, USA; 1961.

  67. 67.

    Hwang J-J, Chow Y-C, Anger FD, Lee C-Y: Scheduling precedence graphs in systems with interprocessor communication times. SIAM Journal on Computing 1989,18(2):244-257. 10.1137/0218016

  68. 68.

    Cai L, Gajski D: Transaction level modeling in system level design. Center for Embedded Computer Systems, Irvine, Calif, USA; 2003.

  69. 69.

    Haverinnen A, Leclercq M, Weyrich N, Wingard D: SystemC based SoC Communication Modeling for the OCP Protocol. Whitepaper, October 2002

  70. 70.

    Bortfeld U, Mielenz C: C++ System Simulation Interfaces. Whitepaper, July 2000

  71. 71.

    Cockx J: Efficient modelling of preemption in a virtual prototype. Proceedings of International Workshop on Rapid System Prototyping (RSP '00), June 2000, Paris, France 14-19.

  72. 72.

    Gupta S, Dutt N, Gupta R, Nciolau A: SPARK: a high-level synthesis framework for applying parallelizing compiler transformations. Proceedings of the 16th International Conference on VLSI Design, January 2003, New Delhi, India 461-466.

  73. 73.

    Guo Y, McChain D, Cavallaro JR: Rapid industrial prototyping and scheduling of 3G/4G SoC architectures with HLS methodology. EURASIP Journal on Embedded Systems 2006., 2006:

  74. 74.

    Valderrama CA, Changuel A, Jerraya AA: Virtual prototyping for modular and flexible hardware-software systems. Design Automation for Embedded Systems 1997,2(3-4):267-282.

Download references

Author information

Correspondence to M Holzer.

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Holzer, M., Knerr, B., Belanović, P. et al. Efficient Design Methods for Embedded Communication Systems. J Embedded Systems 2006, 064913 (2006).

Download citation


  • Design Task
  • Virtual Prototype
  • Signal Processing Algorithm
  • Product Launch
  • Integrate Automation