NoC Design Flow for TDMA and QoS Management in a GALS Context

1. 1.

   Dally WJ, Towles B: Route packets, not wires: on-chip interconnection networks. Proceedings of the 38th Design Automation Conference (DAC '01), June 2001, Las Vegas, Nev, USA 684-689.

   • Google Scholar
2. 2.

   Marescaux T, Bartic A, Verkest D, Vernalde S, Lauwereins R: Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs. Proceedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL '02), September 2002, Montpellier, France 795-805.

   • Google Scholar
3. 3.

   Dally WJ: Interconnect-limited VLSI architecture. Proceedings of IEEE International Conference Interconnect Technology, May 1999, San Francisco, Calif, USA 15-17.

   • Google Scholar
4. 4.

   Evain S, Diguet J-Ph: From NoC security analysis to design solutions. Proceedings of The IEEE Workshop on Signal Processing Systems (SIPS '05), November 2005, Athens, Greece

   • Google Scholar
5. 5.

   Dally WJ: Virtual-channel flow control. IEEE Transactions on Parallel and Distributed Systems 1992,3(2):194-205. 10.1109/71.127260

   • Article
   • Google Scholar
6. 6.

   Bolotin E, Morgenshtein A, Cidon I, Ginosar R, Kolodny A: Automatic hardware-efficient SoC integration by QoS network on chip. Proceedings of the 11th IEEE International Conference on Electronics, Circuits and Systems (ICECS~'04), December 2004, Tel-Aviv, Israel 479-482.

   • Google Scholar
7. 7.

   Goossens K, Dielissen J, van Meerbergen J, et al.: Guaranteeing the quality of services in networks on chip. In Networks on Chip. Edited by: Jantsch A, Tenhunen H. Kluwer Academic, Dordrecht, The Netherlands; 2003:61-82.

   • Google Scholar
8. 8.

   Millberg M, Nilsson E, Thid R, Jantsch A: Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. Proceedings of Design, Automation and Test in Europe (DATE '04), February 2004, Paris, France 2: 890-895.

   • Article
   • Google Scholar
9. 9.

   Carloni LP, Sangiovanni-Vincentelli AL: Coping with latency in SOC design. IEEE Micro 2002,22(5):24-35. special issue on systems on chip 10.1109/MM.2002.1044297

   • Article
   • Google Scholar
10. 10.

    Lines A: Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs. Proceedings of the 11th Symposium on High Performance Interconnects, August 2003, Stanford, Calif, USA 2-9.

    • Google Scholar
11. 11.

    Arteris, http://www.arteris.net

12. 12.

    Beigné E, Clermidy F, Vivet P, Clouard A, Renaudin M: An asynchronous NOC architecture providing low latency service and its multi-level design framework. Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '05), March 2005, New York, NY, USA 54-63.

    • Google Scholar
13. 13.

    Bjerregaard T, Sparsø J: A scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip. Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '05), March 2005, New York, NY, USA 34-43.

    • Google Scholar
14. 14.

    Hillman D: Using mobilize power management IP for dynamic & static power reduction in SoC at 130 nm. Proceedings of Design, Automation and Test in Europe (DATE '05), March 2005, Munich, Germany 3: 240-246.

    • Article
    • Google Scholar
15. 15.

    Rijpkema E, Goossens K, Rădulescu A, et al.: Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. Proceedings of Design Automation and Test Conference in Europe (DATE '03), March 2003, Munich, Germany 350-355.

    • Google Scholar
16. 16.

    Rǎdulescu A, Dielissen J, Goossens K, Rijpkema E, Wielage P: An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration. Proceedings of Design, Automation and Test in Europe (DATE '04), February 2004, Paris, France 2: 878-883.

    • Article
    • Google Scholar
17. 17.

    Evain S, Diguet J-Ph, Houzet D: A generic CAD tool for efficient NoC design. Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS '04), November 2004, Seoul, Korea 728-733.

    • Google Scholar

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