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NoC Design Flow for TDMA and QoS Management in a GALS Context

EURASIP Journal on Embedded Systems volume 2006, Article number: 063656 (2006) Cite this article

Abstract

This paper proposes a new approach dealing with the tedious problem of NoC guaranteed traffics according to GALS constraints impelled by the upcoming large System-on-Chips with multiclock domains. Our solution has been designed to adjust a tradeoff between synchronous and clockless asynchronous techniques. By means of smart interfaces between synchronous sub-NoCs, Quality-of-Service (QoS) for guaranteed traffic is assured over the entire chip despite clock heterogeneity. This methodology can be easily integrated in the usual NoC design flow as an extension to traditional NoC synchronous design flows. We present real implementation obtained with our tool for a 4G telecom scheme.

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Authors and Affiliations

  1. LESTER, UBS/CNRS, Centre de recherché, BP 92116, Lorient Cedex, 56321, France

    Samuel Evain & Jean-Philippe Diguet

  2. IETR, INSA/CNRS, 20 Avenue des Buttes de Coësmes, Rennes Cedex, 35043, France

    Dominique Houzet

Authors
  1. Samuel Evain
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  2. Jean-Philippe Diguet
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  3. Dominique Houzet
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Correspondence to Samuel Evain.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Evain, S., Diguet, JP. & Houzet, D. NoC Design Flow for TDMA and QoS Management in a GALS Context. J Embedded Systems 2006, 063656 (2006). https://doi.org/10.1155/ES/2006/63656

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  • DOI: https://doi.org/10.1155/ES/2006/63656

Keywords

  • Assure
  • Control Structure
  • Electronic Circuit
  • Design Flow
  • Real Implementation