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EURASIP Journal on Embedded Systems
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  • Research Article
  • Open Access

NoC Design Flow for TDMA and QoS Management in a GALS Context

EURASIP Journal on Embedded Systems20062006:063656

https://doi.org/10.1155/ES/2006/63656

©  Samuel Evain et al. 2006

  • Received: 15 December 2005
  • Accepted: 5 August 2006
  • Published:

Abstract

This paper proposes a new approach dealing with the tedious problem of NoC guaranteed traffics according to GALS constraints impelled by the upcoming large System-on-Chips with multiclock domains. Our solution has been designed to adjust a tradeoff between synchronous and clockless asynchronous techniques. By means of smart interfaces between synchronous sub-NoCs, Quality-of-Service (QoS) for guaranteed traffic is assured over the entire chip despite clock heterogeneity. This methodology can be easily integrated in the usual NoC design flow as an extension to traditional NoC synchronous design flows. We present real implementation obtained with our tool for a 4G telecom scheme.

Keywords

  • Assure
  • Control Structure
  • Electronic Circuit
  • Design Flow
  • Real Implementation

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Authors’ Affiliations

(1)
LESTER, UBS/CNRS, Centre de recherché, BP 92116, Lorient Cedex, 56321, France
(2)
IETR, INSA/CNRS, 20 Avenue des Buttes de Coësmes, Rennes Cedex, 35043, France

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Copyright

© Samuel Evain et al. 2006

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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