Open Access

MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution

EURASIP Journal on Embedded Systems20062006:054074

https://doi.org/10.1155/ES/2006/54074

Received: 15 December 2005

Accepted: 2 June 2006

Published: 12 October 2006

Abstract

Fully integrated system level design space exploration methodologies are essential to guarantee efficiency of future large scale system on programmable chip. Each design step in the design flow from system architecture to place and route represents an optimization problem. So far, different tools (computer architecture, design automation) are used to address each problem separately with at best estimation techniques from one level to another. This approach ignores the various and very diverse vertical relations between distinct levels parameters and provides at best local optimization solutions at each step. Due to the large scale of SoC, system level design methodologies need to tackle the system design process as a global optimization problem by fully integrating physical design in the design space exploration. We propose MOCDEX, a multiobjective design space exploration methodology, for multiprocessor on chip which closes the gap between these associated tools in a fully integrated approach and with hardware in the loop. A case study of a 4-way multiprocessor demonstrates the validity of our approach.

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Authors’ Affiliations

(1)
UEI

References

  1. Alpha-Data ADM-XRC-II PCI mezzanine card, http://www.alpha-data.com
  2. Aouadi I, Mouhoub RB, Hammami O: System on a programmable chip oriented JPEG-2000 entropy coder implementation for multimedia embedded systems. Proceedings of the IEEE International Conference on Consumer Electronics (ICCE '05), January 2005, Las Vegas, Nev, USA 447-448.Google Scholar
  3. Bambha NK, Bhattacharyya SS: Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors. IEEE Transactions on Parallel and Distributed Systems 2005,16(2):99-112.View ArticleGoogle Scholar
  4. Coello CAC: An updated survey of GA-based multiobjective optimization techniques. ACM Computing Surveys 2000,32(2):109-143. 10.1145/358923.358929View ArticleGoogle Scholar
  5. Coello CAC, Veldhuizen DV, Lamont GB: Evolutionary Algorithms for Solving Multi-Objective Problems, Genetic Algorithms and Evolutionary Computation. Volume 5. Kluwer Academic, Dordrecht, The Netherlands; 2002.View ArticleGoogle Scholar
  6. Culler D, Singh JP, Gupta A: Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann, San Francisco, Calif, USA; 1999.Google Scholar
  7. Deb K, Pratap A, Agarwal S, Meyarivan T: A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Transactions on Evolutionary Computation 2002,6(2):182-197. 10.1109/4235.996017View ArticleGoogle Scholar
  8. Fummi F, Martini S, Perbellini G, Poncino M: Native ISS-SystemC integration for the co-simulation of multi-processor SoC. Proceedings of the IEEE Conference and Exhibition on Design, Automation and Test in Europe (DATE '04), February 2004, Paris, France 1: 564-569.View ArticleGoogle Scholar
  9. Ghali K, Hammami O: Embedded processor characteristics specification through multiobjective evolutionary algorithms. Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE '03), June 2003, Rio de Janeiro, Brazil 2: 907-912.Google Scholar
  10. Ghali K, Hammami O: Embedded processors optimization with hardware in the loop. Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE '04), May 2004, Ajaccio, France 1: 561-564.Google Scholar
  11. Ghenassia F: Transaction-Level Modeling with SystemC TLM Concepts and Applications for Embedded Systems. Springer, New York, NY, USA; 2005.View ArticleGoogle Scholar
  12. Jensen MT: Reducing the run-time complexity of multiobjective EAs: the NSGA-II and other algorithms. IEEE Transactions on Evolutionary Computation 2003,7(5):503-515. 10.1109/TEVC.2003.817234View ArticleGoogle Scholar
  13. Jerraya AA, Wolf W: Multiprocessor Systems-on-Chips. Morgan Kaufman, San Francisco, Calif, USA; 2004.Google Scholar
  14. Jin Y, Satish N, Ravindran K, Keutzer K: An automated exploration framework for FPGA-based soft multiprocessor systems. Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES '05), September 2005, New York, NY, USA 273-278.Google Scholar
  15. Keating M, Bricaud P: Reuse Methodology Manual for System-on-a-Chip Designs. Springer, New York, NY, USA; 2002.Google Scholar
  16. Lyonnard D, Yoo S, Baghdadi A, Jerraya AA: Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip. Proceedings of the 38th Design Automation Conference (DAC '01), June 2001, Las Vegas, Nev, USA 518-523.Google Scholar
  17. Mouhoub RB, Aouadi I, Hammami O: System on programmable chip platform based design of JPEG- 2000 entropy coder. Proceedings of the 12th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '04), October 2004, Kanazawa, Japan 103-106.Google Scholar
  18. Sun F, Ravi S, Raghunathan A, Jha NK: Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors. Proceedings of the 18th IEEE International Conference on VLSI Design, January 2005, Kolkata, India 551-556.Google Scholar
  19. Xilinx Embedded system tools guide, http://www.xilinx.com/ise/embedded/edk_docs.htm
  20. Xilinx microblaze soft core processor, http://www.xilinx.com/ise/embedded/mb_refguide
  21. Xilinx Fast Simplex Link IP, http://www.xilinx.com
  22. Xilinx Virtex-II Platform FPGA, http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex_ii_platform_fpgas/index.htm

Copyright

© R. B. Mouhoub and O. Hammami. 2006

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.