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Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems

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Abstract

Automotive, avionic, or body-area networks are systems that consist of several communicating control units specialized for certain purposes. Typically, different constraints regarding fault tolerance, availability and also flexibility are imposed on these systems. In this article, we will present a novel framework for increasing fault tolerance and flexibility by solving the problem of hardware/software codesign online. Based on field-programmable gate arrays (FPGAs) in combination with CPUs, we allow migrating tasks implemented in hardware or software from one node to another. Moreover, if not enough hardware/software resources are available, the migration of functionality from hardware to software or vice versa is provided. Supporting such flexibility through services integrated in a distributed operating system for networked embedded systems is a substantial step towards self-adaptive systems. Beside the formal definition of methods and concepts, we describe in detail a first implementation of a reconfigurable networked embedded system running automotive applications.

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References

  1. 1.

    Walder H, Platzner M: Online scheduling for block-partitioned reconfigurable devices. Proceedings of Design, Automation and Test in Europe (DATE '03), March 2003, Munich, Germany 290-295.

  2. 2.

    Ahmadinia A, Bobda C, Koch D, Majer M, Teich J: Task scheduling for heterogeneous reconfigurable computers. Proceedings of the 17th Symposium on Integrated Cicuits and Systems Design (SBCCI '04), September 2004, Pernambuco, Brazil 22-27.

  3. 3.

    Ahmadinia A, Bobda C, Teich J: On-line placement for dynamically reconfigurable devices. International Journal of Embedded Systems 2006,1(3/4):165-178. 10.1504/IJES.2005.009947

  4. 4.

    Lysecky R, Vahid F: A configurable logic architecture for dynamic hardware/software partitioning. Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '04), February 2004, Paris, France 1: 480-485.

  5. 5.

    Baumgarte V, May F, Nückel A, Vorbach M, Weinhardt M: PACT XPP—a self-reconfigurable data processing architecture. Proceedings of 1st International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '01), June 2001, Las Vegas, Nev, USA

  6. 6.

    Chameleon Systems CS2000 Reconfigurable Communications Processor, Family Product Brief, 2000

  7. 7.

    Thomas A, Becker J: Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur. Proceedings of Organic and Pervasive Computing, Workshops (ARCS '04), March 2004, Augsburg, Germany 165-174.

  8. 8.

    Bobda C, Koch D, Majer M, Ahmadinia A, Teich J: A dynamic NoC approach for communication in reconfigurable devices. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL '04), August-September 2004, Antwerp, Belgium 1032-1036.

  9. 9.

    Altera : FLEX 10K Devices. November 2005, http://www.altera.com/products/devices/flex10k/f10-index.html

  10. 10.

    Zipf P: A fault tolerance technique for field- programmable logic arrays, M.S. thesis. Siegen University, Siegen, Germany; 2002.

  11. 11.

    Doumar A, Ito H: Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. IEEE Transactions on Very Large Scale Integration Systems 2003,11(3):386-405. 10.1109/TVLSI.2002.801609

  12. 12.

    CERN : FPGA Dynamic Reconfiguration in ALICE and beyond. November 2005, http://alicedcs.web.cern.ch/alicedcs/

  13. 13.

    Xu W, Ramanarayanan R, Tessier R: Adaptive fault recovery for networked reconfigurable systems. In Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '03), April 2003, Los Alamitos, Calif, USA. IEEE Computer Society; 143.

  14. 14.

    Lach J, Mangione-Smith WH, Potkonjak M: Efficiently supporting fault-tolerance in FPGAs. In Proceedings of the ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays (FPGA '98), February 1998, Monterey, Calif, USA. ACM Press; 105-115.

  15. 15.

    Huang W-J, McCluskey EJ: Column-based precompiled configuration techniques for FPGA. In Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '01), April-May 2001, Rohnert Park, Calif, USA. IEEE Computer Society; 137-146.

  16. 16.

    Elnozahy EN, Alvisi L, Wang Y-M, Johnson DB: A survey of rollback-recovery protocols in message-passing systems. ACM Computing Surveys 2002,34(3):375-408. 10.1145/568522.568525

  17. 17.

    Chandy KM, Lamport LM: Distributed snapshots: determining global states of distributed systems. ACM Transactions on Computer Systems 1985,3(1):63-75. 10.1145/214451.214456

  18. 18.

    Vaidya NH: Impact of checkpoint latency on overhead ratio of a checkpointing scheme. IEEE Transactions on Computers 1997,46(8):942-947. 10.1109/12.609281

  19. 19.

    Poledna S: Fault-Tolerant Real-Time Systems: The Problem of Replica Determinism. Kluwer Academic, Boston, Mass, USA; 1996.

  20. 20.

    Trimberger S, Carberry D, Johnson A, Wong J: A time-multiplexed FPGA. In Proceedings of 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), April 1997, Napa Valley, Calif, USA. IEEE Computer Society; 22-29.

  21. 21.

    Scalera SM, Vázquez JR: The design and implementation of a context switching FPGA. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '98), April 1998, Napa, Calif, USA. IEEE Computer Society; 78.

  22. 22.

    Puttegowda K, Lehn DI, Park JH, Athanas P, Jones M: Context switching in a run-time reconfigurable system. Journal of Supercomputing 2003,26(3):239-257. 10.1023/A:1025694914489

  23. 23.

    Brebner G: The swappable logic unit: a paradigm for virtual hardware. In Proceedings IEEE Symposium on FPGAs for Custom Computing Machines, April 1997, Napa Valley, Calif, USA. Edited by: Pocek KL, Arnold J. IEEE Computer Press; 77-86.

  24. 24.

    Simmler H, Levinson L, Männer R: Multitasking on FPGA coprocessors. Proceedings of the 10th International Workshop on Field-Programmable Logic and Applications (FPL '00), August 2000, Villach, Austria 121-130.

  25. 25.

    Simmler H: Preemptive Multitasking auf FPGA Prozessoren, Dissertation. University of Mannheim, Mannheim, Germany; 2001. page 279

  26. 26.

    Buttazzo GC: Hard Real-Time Computing Systems. Kluwer Academic, Boston, Mass, USA; 2002.

  27. 27.

    Blickle T, Teich J, Thiele L: System-level synthesis using evolutionary algorithms. In Design Automation for Embedded Systems. Volume 3. Edited by: Gupta R. Kluwer Academic, Boston, Mass, USA; 1998:23-62. 10.1023/A:1008899229802

  28. 28.

    Koch D, Streichert T, Dittrich S, Strengert C, Haubelt CD, Teich J: An operating system infrastructure for fault-tolerant reconfigurable networks. Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS '06), March 2006, Frankfurt/Main, Germany 202-216.

  29. 29.

    Bazargan K, Kastner R, Sarrafzadeh M: Fast template placement for reconfigurable computing systems. IEEE Design and Test of Computers 2000,17(1):68-83. 10.1109/54.825678

  30. 30.

    Walder H, Platzner M: Fast online task placement on FPGAs: free space partitioning and 2D-hashing. Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS '03) /Reconfigurable Architectures Workshop (RAW '03), April 2003, Nice, France 178.

  31. 31.

    Cybenko G: Dynamic load balancing for distributed memory multiprocessors. Journal of Parallel and Distributed Computing 1989,7(2):279-301. 10.1016/0743-7315(89)90021-X

  32. 32.

    Streichert T, Haubelt CD, Teich J: Distributed HW/SW-partitioning for embedded reconfigurable systems. Proceedings of Design, Automation and Test in Europe Conference and Exposition (DATE '05), March 2005, Munich, Germany 894-895.

  33. 33.

    Streichert T, Haubelt CD, Teich J: Online hardware/software partitioning in networked embedded systems. Proceedings of Asia South Pacific Design Automation Conference (ASP-DAC '05), January 2005, Shanghai, China 982-985.

  34. 34.

    Horta EL, Lockwood JW, Kofuji ST: Using parbit to implement partial run-time reconfigurable systems. In Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications (FPL '02), September 2002, Montpellier, France. Springer; 182-191.

  35. 35.

    Kalte H, Lee G, Porrmann M, Rückert U: REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems. Proceedings of 19th IEEE International Parallel and Distributed Processing Symposium—Reconfigurable Architectures Workshop, April 2005, Denver, Colo, USA 151.

  36. 36.

    OpenCores 2005, http://www.opencores.org

  37. 37.

    Altera : Nios II Processor Reference Handbook. July 2005

  38. 38.

    Labrosse J: Micro-C/OS-II. 2nd edition. CMP Books, Gilroy, Calif, USA; 2002.

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Correspondence to Thilo Streichert.

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Keywords

  • Migration
  • Operating System
  • Control Unit
  • Control Structure
  • Fault Tolerance