Open Access

Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC

  • Ari Kulmala1Email author,
  • Olli Lehtoranta1,
  • TimoD Hämäläinen1 and
  • Marko Hännikäinen1
EURASIP Journal on Embedded Systems20062006:038494

https://doi.org/10.1155/ES/2006/38494

Received: 15 December 2005

Accepted: 27 June 2006

Published: 2 October 2006

Abstract

High computational requirements combined with rapidly evolving video coding algorithms and standards are a great challenge for contemporary encoder implementations. Rapid specification changes prefer full programmability and configurability both for software and hardware. This paper presents a novel scalable MPEG-4 video encoder on an FPGA-based multiprocessor system-on-chip (MPSOC). The MPSOC architecture is truly scalable and is based on a vendor-independent intellectual property (IP) block interconnection network. The scalability in video encoding is achieved by spatial parallelization where images are divided to horizontal slices. A case design is presented with up to four synthesized processors on an Altera Stratix 1S40 device. A truly portable ANSI-C implementation that supports an arbitrary number of processors gives 11 QCIF frames/s at 50 MHz without processor specific optimizations. The parallelization efficiency is 97% for two processors and 93% with three. The FPGA utilization is 70%, requiring 28 797 logic elements. The implementation effort is significantly lower compared to traditional multiprocessor implementations.

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Authors’ Affiliations

(1)
Department of Information Technology, Institute of Digital and Computer Systems, Tampere University of Technology

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Copyright

© Ari Kulmala et al. 2006

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.