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Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC


High computational requirements combined with rapidly evolving video coding algorithms and standards are a great challenge for contemporary encoder implementations. Rapid specification changes prefer full programmability and configurability both for software and hardware. This paper presents a novel scalable MPEG-4 video encoder on an FPGA-based multiprocessor system-on-chip (MPSOC). The MPSOC architecture is truly scalable and is based on a vendor-independent intellectual property (IP) block interconnection network. The scalability in video encoding is achieved by spatial parallelization where images are divided to horizontal slices. A case design is presented with up to four synthesized processors on an Altera Stratix 1S40 device. A truly portable ANSI-C implementation that supports an arbitrary number of processors gives 11 QCIF frames/s at 50 MHz without processor specific optimizations. The parallelization efficiency is 97% for two processors and 93% with three. The FPGA utilization is 70%, requiring 28 797 logic elements. The implementation effort is significantly lower compared to traditional multiprocessor implementations.

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  1. Agi I, Jagannathan R: A portable fault-tolerant parallel software MPEG-1 encoder. Multimedia Tools and Applications 1996,2(3):183-197.

    Google Scholar 

  2. Ahmad I, He Y, Liou ML: Video compression with parallel processing. Parallel Computing 2002,28(7-8):1039-1078. 10.1016/S0167-8191(02)00100-X

    Article  MATH  Google Scholar 

  3. Akramullah SM, Ahmad I, Liou ML: Performance of software-based MPEG-2 video encoder on parallel and distributed systems. IEEE Transactions on Circuits and Systems for Video Technology 1997,7(4):687-695. Transaction Briefs 10.1109/76.611179

    Article  Google Scholar 

  4. Altera Corporation : Avalon Interface Specification. Ver. 2.4, January 2004

  5. Altera Corporation : Nios 3.0 CPU datasheet. October 2004

  6. Altera Corporation : Nios Development Board: Reference Manual, Stratix Professional Edition. Ver. 1.1, July 2003

  7. Altera Corporation : Nios II Processor Reference Handbook. May 2005

  8. Altera Corporation : Stratix Device Handbook. January 2005

  9. Altera Corporation Nios II, Site visited 28.11.2005,

  10. Barbosa DM, Kitajima JP, Weira W Jr.: Parallelizing MPEG video encoding using multiprocessors. Proceedings of the XII Brazilian Symposium on Computer Graphics and Image Processing (SIBGRAPI '99), October 1999, Sao Paulo, Brazil 215-222.

    Google Scholar 

  11. Cantineau O, Legat J-D: Efficient parallelisation of an MPEG-2 codec on a TMS320C80 video processor. IEEE International Conference on Image Processing (ICIP '98), October 1998, Chicago, Ill, USA 3: 977-980.

    Article  Google Scholar 

  12. Garrido MJ, Sanz C, Jiménez M, Menasses JM: An FPGA implementation of a flexible architecture for H.263 video coding. IEEE Transactions on Consumer Electronics 2002,48(4):1056-1066. 10.1109/TCE.2003.1196439

    Article  Google Scholar 

  13. He Y, Ahmad I, Liou ML: MPEG-4 based interactive video using parallel processing. International Conference on Parallel Processing (ICPP '98), August 1998, Minneapolis, Minn, USA 329-336.

    Google Scholar 

  14. Kalte H, Langen D, Vonnahme E, Brinkmann A, Rückert U: Dynamically reconfigurable system-on-programmable-chip. 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing (PDP '02), January 2002, Canary Islands, Spain 235-242.

    Chapter  Google Scholar 

  15. Kordasiewicz R, Shirani S: Hardware implementation of the optimized transform and quantization blocks of H.264. Canadian Conference on Electrical and Computer Engineering (CCECE '04), May 2004, Niagara Falls, Ontario, Canada 2: 943-946.

    Google Scholar 

  16. Kuhn P: Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation. Kluwer Academic, Dordrecht, The Netherlands; 1999.

    Book  MATH  Google Scholar 

  17. Kulmala A, Salminen E, Lehtoranta O, Hämäläinen TD, Hännikäinen M: Impact of shared instruction memory on performance of FPGA-based MP-SoC video encoder. The 9th IEEE workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS '06), April 2006, Prague, Czech Republic 59-64.

    Google Scholar 

  18. Lehtoranta O, Hämäläinen TD: Feasibility study of a real-time operating system for a multichannel MPEG-4 encoder. Multimedia on Mobile Devices, January 2005, San Jose, Calif, USA, Proceedings of SPIE 5684: 292-299.

    Article  Google Scholar 

  19. Lehtoranta O, Hämäläinen TD, Lappalainen V, Mustonen J: Parallel implementation of video encoder on quad DSP system. Microprocessors and Microsystems 2002,26(1):1-15. 10.1016/S0141-9331(01)00141-7

    Article  Google Scholar 

  20. Lehtoranta O, Salminen E, Kulmala A, Hännikäinen M, Hämäläinen TD: A parallel MPEG-4 encoder for FPGA based multiprocessor SoC. 15th International Conference on Field Programmable Logic and Applications (FPL '05), August 2005, Tampere, Finland 380-385.

    Google Scholar 

  21. Lin Y-L, Young C-P, Chang Y-J, Chung Y-H, Su AWY: Versatile PC/FPGA based verification/fast prototyping platform with multimedia applications. Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference (IMTC '04), May 2004, Como, Italy 2: 1490-1495.

    Article  Google Scholar 

  22. Martina M, Molino A, Vacca F: FPGA system-on-chip soft IP design: a reconfigurable DSP. Proceedings of the 45th Midwest Symposium on Circuits and Systems (MWSCAS '02), August 2002, Tulsa, Okla, USA 3: 196-199.

    Google Scholar 

  23. Nang J, Kim J: An Effective parallelizing scheme of MPEG-1 video encoding on ethernet-connected workstations. Proceedings of the Conference on Advances in Parallel and Distributed Computing (APDC '97), March 1997, Shanghai, China 4-11.

    Chapter  Google Scholar 

  24. OCP-IP Alliance : Open Core Protocol specification. Release 2.0, 2003

  25. Peng Q, Jing J: H.264 codec system-on-chip design and verification. 5th International Conference on ASIC (ASICON '03), October 2003, Beijing, China 2: 922-925.

    Google Scholar 

  26. Peng Q, Zhao Y: Study on parallel approach in H.26L video encoder. 4th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT '03), August 2003, Chengdu, China 834-837.

    Google Scholar 

  27. Salminen E, Kangas T, Riihimäki J, Lahtinen V, Kuusilinna K, Hämäläinen TD: HIBI v.2 communication network for system-on-chip. In Computer Systems: Architectures, Modeling, and Simulation, Lecture Notes in Computer Science. Volume 3133. Edited by: Pimentel AD, Vassiliadis S. Springer, Berlin, Germany; 2004:412-422.

    Google Scholar 

  28. Salminen E, Kulmala A, Hämäläinen TD: HIBI-based multiprocessor SoC on FPGA. IEEE International Symposium on Circuits and Systems (ISCAS '05), May 2005, Kobe, Japan 3351-3354.

    Google Scholar 

  29. Wang X, Ziavras SG: Parallel direct solution of linear equations of FPGA-based machines. IEEE International Parallel & Distributed Processing Symposium (IPDPS '03), April 2003, Nice, France 113-120.

    Google Scholar 

  30. Yung NHC, Leung K-K: Spatial and temporal data parallelization of the H.261 video coding algorithm. IEEE Transactions on Circuits and Systems for Video Technology 2001,11(1):91-104. 10.1109/76.894289

    Article  Google Scholar 

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Correspondence to Ari Kulmala.

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Kulmala, A., Lehtoranta, O., Hämäläinen, T. et al. Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC. J Embedded Systems 2006, 038494 (2006).

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  • Video Code
  • Code Algorithm
  • Video Encode
  • Horizontal Slice
  • Spatial Parallelization