- Research Article
- Open Access
FPGA Dynamic Power Minimization through Placement and Routing Constraints
EURASIP Journal on Embedded Systemsvolume 2006, Article number: 031605 (2006)
Field-programmable gate arrays (FPGAs) are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR) tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE) is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuits mapped into 0.12 μ m Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.
Anderson JH, Najm FN, Tuan T: Active leakage power optimization for FPGAs. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '04), February 2004, Monterey, Calif, USA 12: 33-41.
French M: A power efficient image convolution engine for field programmable gate arrays. 7th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD '04), September 2004, Washington, DC, USA
Anderson JH, Najm FN: A novel low-power FPGA routing switch. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '04), October 2004, Orlando, Fla, USA 719-722.
Kusse E, Rabaey J: Low-energy embedded FPGA structures. Proceedings of the International Symposium on Low Power Electronics and Design, August 1998, Monterey, Calif, USA 155-160.
Anderson JH, Najm FN: Power-aware technology mapping for LUT-based FPGAs. IEEE International Conference on Field-Programmable Technology (FPT '02), December 2002, Hong Kong 211-218.
Rollins N, Wirthlin MJ: Reducing energy in FPGA multipliers through glitch reduction. 7th Annual International Conference on Military Applications of Programmable Logic Devices (MAPLD '05), September 2005, Washington, DC, USA
Lamoureux J, Wilton SJE: On the interaction between power-aware FPGA CAD algorithms. IEEE/ACM International Conference on Computer-Aided Design (ICCAD '03), November 2003, San Jose, Calif, USA 701-708.
Shang L, Kaviani AS, Bathala K: Dynamic power consumption in virtex-II FPGA family. Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '02), February 2002, Monterey, Calif, USA 157-164.
Virtex-II Platform FPGAs: Complete Data Sheet http://www.xilinx.com
Xilinx ISE Software Manual http://www.xilinx.com
French M, Wang L, Anderson T, Wirthlin M: Post synthesis level power modeling of FPGAs. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '05), April 2005, Napa, Calif, USA 281-282.