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Fixed-Point Configurable Hardware Components

EURASIP Journal on Embedded Systems volume 2006, Article number: 023197 (2006) Cite this article

Abstract

To reduce the gap between the VLSI technology capability and the designer productivity, design reuse based on IP (intellectual properties) is commonly used. In terms of arithmetic accuracy, the generated architecture can generally only be configured through the input and output word lengths. In this paper, a new kind of method to optimize fixed-point arithmetic IP has been proposed. The architecture cost is minimized under accuracy constraints defined by the user. Our approach allows exploring the fixed-point search space and the algorithm-level search space to select the optimized structure and fixed-point specification. To significantly reduce the optimization and design times, analytical models are used for the fixed-point optimization process.

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Authors and Affiliations

  1. ENSSAT, Université de Rennes 1, 6 rue de Kerampont, Lannion, 22305, France

    Romuald Rocher, Daniel Menard, Nicolas Herve & Olivier Sentieys

  2. IRISA, Université de Rennes 1, Campus de Beaulieu, Rennes, 35042, France

    Romuald Rocher, Daniel Menard, Nicolas Herve & Olivier Sentieys

Authors
  1. Romuald Rocher
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  2. Daniel Menard
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  3. Nicolas Herve
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  4. Olivier Sentieys
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Correspondence to Romuald Rocher.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Rocher, R., Menard, D., Herve, N. et al. Fixed-Point Configurable Hardware Components. J Embedded Systems 2006, 023197 (2006). https://doi.org/10.1155/ES/2006/23197

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