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A Reconfigurable FPGA System for Parallel Independent Component Analysis
EURASIP Journal on Embedded Systems volume 2006, Article number: 023025 (2006)
A run-time reconfigurable field programmable gate array (FPGA) system is presented for the implementation of the parallel independent component analysis (ICA) algorithm. In this work, we investigate design challenges caused by the capacity constraints of single FPGA. Using the reconfigurability of FPGA, we show how to manipulate the FPGA-based system and execute processes for the parallel ICA (pICA) algorithm. During the implementation procedure, pICA is first partitioned into three temporally independent function blocks, each of which is synthesized by using several ICA-related reconfigurable components (RCs) that are developed for reuse and retargeting purposes. All blocks are then integrated into a design and development environment for performing tasks such as FPGA optimization, placement, and routing. With partitioning and reconfiguration, the proposed reconfigurable FPGA system overcomes the capacity constraints for the pICA implementation on embedded systems. We demonstrate the effectiveness of this implementation on real images with large throughput for dimensionality reduction in hyperspectral image (HSI) analysis.
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Du, H., Qi, H. A Reconfigurable FPGA System for Parallel Independent Component Analysis. J Embedded Systems 2006, 023025 (2006). https://doi.org/10.1155/ES/2006/23025
- Dimensionality Reduction
- Independent Component Analysis
- Embed System
- Field Programmable Gate Array
- Capacity Constraint