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Generation of Embedded Hardware/Software from SystemC

EURASIP Journal on Embedded Systems volume 2006, Article number: 018526 (2006) Cite this article

Abstract

Designers increasingly rely on reusing intellectual property (IP) and on raising the level of abstraction to respect system-on-chip (SoC) market characteristics. However, most hardware and embedded software codes are recoded manually from system level. This recoding step often results in new coding errors that must be identified and debugged. Thus, shorter time-to-market requires automation of the system synthesis from high-level specifications. In this paper, we propose a design flow intended to reduce the SoC design cost. This design flow unifies hardware and software using a single high-level language. It integrates hardware/software (HW/SW) generation tools and an automatic interface synthesis through a custom library of adapters. We have validated our interface synthesis approach on a hardware producer/consumer case study and on the design of a given software radiocommunication application.

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Authors and Affiliations

  1. Institut d'Electronique et de Télécommunications de Rennes (IETR), UMR CNRS 6164, Institut National des Sciences Appliquées (INSA), 20 avenue des Buttes de Coësmes, Rennes Cedex, 35043, France

    Salim Ouadjaout & Dominique Houzet

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  1. Salim Ouadjaout
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  2. Dominique Houzet
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Correspondence to Salim Ouadjaout.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Ouadjaout, S., Houzet, D. Generation of Embedded Hardware/Software from SystemC. J Embedded Systems 2006, 018526 (2006). https://doi.org/10.1155/ES/2006/18526

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