- Research Article
- Open Access
Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology
EURASIP Journal on Embedded Systemsvolume 2006, Article number: 014952 (2006)
Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial rapid prototyping experiences on 3G/4G wireless systems using advanced signal processing algorithms in MIMO-CDMA and MIMO-OFDM systems. Core system design issues are studied and advanced receiver algorithms suitable for implementation are proposed for synchronization, MIMO equalization, and detection. We then present VLSI-oriented complexity reduction schemes and demonstrate how to interact these high-complexity algorithms with an HLS-based methodology for extensive design space exploration. This is achieved by abstracting the main effort from hardware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology. Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market for wireless systems.
Wiesel A, García L, Vidal J, Pagès A, Fonollosa JR: Turbo linear dispersion space time coding for MIMO HSDPA systems. Proceedings of 12th IST Summit on Mobile and Wireless Communications, June 2003, Aveiro, Portugal
Golden GD, Foschini CJ, Valenzuela RA, Wolniansky PW: Detection algorithm and initial laboratory results using V-BLAST space-time communication architecture. Electronics Letters 1999,35(1):14-16. 10.1049/el:19990058
Foschini GJ: Layered space-time architecture for wireless communication in a fading environment when using multi-element antennas. Bell Labs Technical Journal 1996,1(2):41-59. 10.1002/bltj.2015
Guo Y, Zhang J, McCain D, Cavallaro JR: Efficient MIMO equalization for downlink multi-code CDMA: complexity optimization and comparative study. Proceedings of IEEE Global Telecommunications Conference (GLOBECOM '04), November-December 2004, Dallas, Tex, USA 4: 2513-2519.
Yue J, Kim KJ, Gibson JD, Iltis RA: Channel estimation and data detection for MIMO-OFDM systems. Proceedings of IEEE Global Telecommunications Conference (GLOBECOM '03), December 2003, San Francisco, Calif, USA 2: 581-585.
Lee Y, Jain VK: VLSI architecture for an advance DS/CDMA wireless communication receiver. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon, October 1997, Austin, Tex, USA 237-247.
Guo Z, Nilsson P: An ASIC implementation for V-BLAST detection in 0.35 μm CMOS. Proceedings of the 4th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT '04), December 2004, Rome, Italy 95-98.
Adjoudani A, Beck EC, Burg AP, et al.: Prototype experience for MIMO BLAST over third-generation wireless system. IEEE Journal on Selected Areas in Communications 2003,21(3):440-451. 10.1109/JSAC.2003.809724
Razavi B: RF Microelectronics, Prentice Hall Communications Engineering and Emerging Technologies Series. Prentice-Hall, Upper Saddle River, NJ, USA; 1998.
Hooli K, Juntti M, Heikkilä MJ, Komulainen P, Latva-Aho M, Lilleberg J: Chip-level channel equalization in WCDMA downlink. EURASIP Journal on Applied Signal Processing 2002,2002(8):757-770. 10.1155/S1110865702000914
Rabaey JM: Low-power silicon architecture for wireless communications: embedded tutorial. Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference, January 2000, Yokohama, Japan 377-380.
Evans A, Silburt A, Vrckovnik G, et al.: Functional verification of large ASICs. Proceedings of 35th ACM/IEEE Design Automation Conference (DAC '98), June 1998, San Francisco, Calif, USA 650-655.
Bhasker J: A VHDL Primer. 3rd edition. Prentice-Hall, Upper Saddle River, NJ, USA; 1999.
Camposano R, Wolf W: Trends in High-Level Synthesis. Kluwer, Boston, Mass, USA; 1991.
De Micheli G, Ku DC: HERCULES - a system for high-level synthesis. Proceedings of the 25th ACM/IEEE Conference on Design Automation (DAC '88), June 1988, Anaheim, Calif, USA 483-488.
Wang C-Y, Parhi KK: High-level DSP synthesis using concurrent transformations, scheduling, and allocation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1995,14(3):274-295. 10.1109/43.365120
Knapp D, Ly T, MacMillen D, Miller R: Behavioral synthesis methodology for HDL-based specification and validation. Proceedings of 32nd ACM Design Automation Conference (DAC '95), June 1995, San Francisco, Calif, USA 286-291.
Weijers J-W, Derudder V, Janssens S, Petré F, Bourdoux A: From MIMO-OFDM algorithms to a real-time wireless prototype: a systematic matlab-to-hardware design flow. EURASIP Journal on Applied Signal Processing 2006, 2006: 12 pages.
Catapult C Manual and C/C++ style guide, Mentor Graphics, 2004
Knippin U: Early design evaluation in hardware and system prototyping for concurrent hardware/software validation in one environment. In Proceedings of 13th IEEE International Workshop on Rapid System Prototyping (RSP '02), July 2002, Darmstadt, Germany. Aptix;
Guo Y, McCain D: Compact hardware accelerator for functional verification and rapid prototyping of 4G wireless communication systems. Proceedings of 38th IEEE Asilomar Conference on Signals, Systems and Computers, November 2004, Pacific Grove, Calif, USA 1: 767-771.
Aulin TM: Breadth-first maximum likelihood sequence detection: basics. IEEE Transactions on Communications 1999,47(2):208-216. 10.1109/26.752126
Golub GH, Loan CFV: Matrix Computations. The Jones Hopkins University Press, Baltimore, Md, USA; 1996.
Rupp M, Burg A, Beck E: Rapid prototyping for wireless designs: the five-ones approach. Signal Processing 2003,83(7):1427-1444. 10.1016/S0165-1684(03)00090-2
Steendam H, Moeneclaey M: The effect of clock frequency offsets on downlink MC-DS-CDMA. Proceedings of IEEE International Symposium on Spread Spectrum Techniques and Applications (ISSSTA '02), September 2002, Prague, Czech Republic 1: 113-117.