# AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic

- Salvatore Levantino
^{1}Email author, - Marco Zanuso
^{1}, - Paolo Madoglio
^{1}, - Davide Tasca
^{1}, - Carlo Samori
^{1}and - AndreaL Lacaita
^{1}

**2010**:175764

https://doi.org/10.1155/2010/175764

© Salvatore Levantino et al. 2010

**Received: **30 June 2009

**Accepted: **23 September 2009

**Published: **12 November 2009

## Abstract

This paper describes the design of an All-Digital Phase Locked Loop (AD-PLL) for wireless applications in the WiMAX 3.3–3.8 GHz bandwidth. The time/digital converter (TDC) sets the in-band noise and it may be responsible for the presence of spurious tones at the PLL output. The TDC is implemented as a delay-locked loop (DLL) to be insensitive to process spreads and it uses a lead-lag phase detector and a digital loop filter to further take advantage of the digital approach. The most important source of spurs is identified in the time skew between counter and TDC in the PLL. This mechanism gives rise to a glitch in the digital feedback signal and spurs in the output spectrum. A simple glitch-corrector logic is described, that completely removes this effect, thus allowing to meet the phase noise specifications. The AD-PLL has been designed in a 90 nm CMOS process.

## Keywords

## 1. Introduction

In recent years, the mixed-signal approach not only has pervaded many applications that once were exclusively a subject for the analog design but also has begun to play an important role also in radiofrequency (RF) front-ends. As a matter of fact, the realization of software defined-radio (SDR) is one of the most important research topic in recent years [1, 2]. In these solutions, digital (or digital-like) circuits are employed not only to calibrate the circuit parameters but also to realize transceiver building blocks, often adopting a new design approach, such as transferring the information processing from the amplitude to the time domain. These techniques, besides increasing the circuit flexibility and functionality, are expected to better exploit the scaling of CMOS technology, to reduce the impact of PVT spreads, to facilitate, at least to a certain extent, the portability of a given design, and to allow for the use of automatic design tools.

The all-digital phase-locked loop (AD-PLL) represents the application of this approach to the design of PLL [3–5]. The digitization of PLL is an old idea, exploited, for instance, in the clock generators for digital circuits. In recent implementations, however, the AD-PLL is employed as frequency synthesizer for wireless systems, which implies tight specification in terms of spectral purity, that is, phase noise and spurs. This fact, for instance, still forces to use an LC-tank oscillator, to ensure the required phase noise performance. The other critical block, concerning the spectral performance, is the time-to-digital converter (TDC). This circuit is essentially the equivalent of an analog-to-digital converter, detecting time (or phase) delays. Of course, it should not rely on standard analog design solutions; otherwise some of the above mentioned advantages will be lost. The TDC is critical in many aspects: it is known that its time resolution affects the in-band noise, while the nonlinearity of its static characteristic can give rise to output spurs [4].

This work presents the design of an AD-PLL for a 3.3–3.8 GHz WiMAX transmitter. In this loop, the TDC is implemented as a digitally-regulated delay line. This is advantageous because of the simplicity of the design, but it requires some care in reducing the generated limit cycle to negligible values.

The unavoidable time skew between the TDC and the counter inputs gives rise to glitches in the AD-PLL feedback signal and ultimately to severe spurious tones in the output spectrum. This effect is not related to our specific implementation of the TDC, but it may affect any common TDC implementations. In this paper, we will show how to predict these skew-induced spurs and we will propose a digital glitch corrector, which is able to operate either when the loop is locked and when the loop is in the lock transient.

In the next Section, the operating principle of the AD-PLL including a counter and a TDC is recalled. Section 3 discusses the advantages of the closed-loop TDC, while Section 4 presents the proposed TDC and explains the presence of the limit cycle in the DLL. Section 5 discusses the generation of glitches in the presence of time skew between counter and TDC. Section 6 proposes a simple glitch-corrector logic. The schematic of the complete AD-PLL is presented in Section 7, together with the simulation results. Finally, the conclusions are drawn in Section 8.

## 2. Combined Operation of TDC and Counter

The error signal at the adder output is given by the difference between FCW and the number of DCO periods occurring within one reference period . The loop forces this error signal to be zero; therefore, if is the DCO frequency, the FCW sets the output frequency as . The signal is a digital number representing the frequency error. This number is then integrated to provide the phase error , whose average is forced to be zero by the loop.

With respect to the original design in [3], the open-loop gain is not altered. The advantage of the structure in Figure 1 is that the design of the adder is simpler since its input word lengths are reduced.

If the FCW were an integer number, only a counter would be necessary in the feedback path. The presence of the TDC is needed because in general FCW may have also a fractional part. For convenience, let us split FCW into two parts: an integer one ( ) and a fractional one ( ). The counter output provides the number of integer DCO periods within , that is, the integer part of the ( / ) ratio. The TDC quantizes the fractional part of ( / ). The lock conditions are and .

At steady state, at each reference edge, the converter count will increment by 2.25 (in our example). Thus, the fractional count will increment by 0.25 and the TDC characteristic will be swept forward. It is easy to see that, in the case of higher than 0.5, the counter would decrease its count by one unity when the differentiated TDC output underflows and the TDC characteristic would be swept backward.

## 3. Closed-Loop TDC

The AD-PLL presented here is intended to be used as a frequency synthesizer in a WiMAX transmitter in the 3.3–3.8 GHz band. In this application, an integral phase noise of about
dBc is required to the synthesizer. According to Figure 2, the TDC quantizes the output phase shifts with a least significant bit (LSB) equal to
, where *τ* is the time resolution of the TDC. This LSB is, in turn, related to the number
of bits of the TDC. Thus,
. The expression of the phase spectrum can be obtained by assuming uniform amplitude distribution and white spectrum for this quantization noise. The resulting quantization noise in the AD-PLL spectrum is
, within the AD-PLL bandwidth. (SSCR is the Single-Sideband to Carrier Ratio.)

Setting this bandwidth to few hundreds of kHz, and the DCO phase noise to dBc/Hz at 1 MHz offset with 1-MHz corner frequency (between and regions), four TDC bits are sufficient to meet the integral phase noise requirements. As a consequence, the delay line needs 16 delay elements and the delay at 3.8 GHz should be about ps. This corresponds to an in-band noise plateau in the PLL spectrum of about dBc/Hz.

In order to meet the noise requirements, the spurious tones need to be lower than dBc.

## 4. DLL-Based TDC

The DAC LSB sets the minimum variation of the cell delay (about 40 fs), which can be considered as the LSB in time domain of the regulation loop. Since the delay line features 16 stages, the delay line can cover a maximum delay variation of (40 fs) (16) ( ) 40 ps. Note that this figure in practice matches the required dynamic of the DLL, which is the difference between the period of the lowest frequency signal (3.3 GHz) and the period of the fastest signal (3.8 GHz). To add some margin for PVT variations, a coarse tuning has been realized by adding three switched capacitors of the same value at the output of each cell. This coarse control is set by the overflow/underflow of the loop integrator.

As shown in Figure 5, the PD operates at the DCO rate (3.3–3.8 GHz). At this frequency, however, the loop filter and the DAC would dissipate an excessive amount of power and the filter would require a custom design. This dissipation can be reduced by noting that no information is lost, if the filter clock is obtained by frequency-division of the DCO signal. In fact, the cell delay, and in turn the PD output, changes only after a variation of the filter output, that is, at the same rate of the digital filter clock. The only disadvantage of this choice is an increase of the DLL lock time. As reasonable trade-off has been found by dividing the input frequency by 8 and limiting the maximum clock frequency below (3.8 GHz)/8 = 475 MHz, this value guarantees at the same time a lock time for the maximum frequency step of about 40 ns, which is less than two reference cycles of the AD-PLL, and the possibility of using standard cells and automatic synthesis tools in the filter design [8].

*t*= the cell delay is below the target delay value; so, the phase detector changes its state and becomes one. This new value is read by the filter at the following clock rising edge and the filter output starts decreasing one clock period later at . Consequently, the cell delay starts to increase. When exceeds the target value (at ), the PD toggles and the dual situation takes place. In practice, the limit cycle period is , where is the filter clock period. The peak-to-peak amplitude of the cycle at the integrator output is 3

*τ*. This behavior is in accordance with the general results presented in [9].

This limit cycle modulates periodically each time bin of the TDC and a spurious tone will appear at both the TDC and the AD-PLL output. Since the limit cycle at is sampled by the TDC flip-flops at , the spurious tones at the TDC output are expected to appear at , with integer . In practice, being , the DCO frequency in the 3.3–3.8-GHz range, and MHz, the spurious tone will fall between about 800 kHz and 11 MHz, depending on the DCO frequency.

## 5. Time Skew in the Counter-TDC Ensemble

The same impairment can be visualized by combining again the TDC and the counter conversion characteristics as shown in Figure 8(b). The effect of the positive time skew is the generation of holes in the characteristic. At steady state, this staircase is swept, going up from one step to another one. Therefore, depending on the initial phase, the converter input may periodically fall into the holes. The resulting phase error is as large as one LSB of the coarse converter, that is, of the counter.

Evaluating the fundamental frequency and the amplitude of the spur in the previous example is particularly simple. Assuming that the spur fundamental falls out of the PLL band, can be calculated following [10]. Thus,

with being the frequency response magnitude of the loop filter and being the DCO frequency resolution.

The example presented here is particularly simple, for the sake of clarity. In particular, the TDC has enough resolution to detect the fractional part of FCW, which makes this case similar to what happens in a standard PLL with an integer division factor. In other cases, the behavior may be slightly more complex; the main issues to be considered are listed as follows:

(i)If is larger than (in our example), the counter sequence will be shifted with respect to the TDC sequence by more than one reference cycle. So, the sequence will include some 0 s between +1 and –1 and its integral will be a sequence of pulses, whose duty cycle depends on the number of 0 s in the sequence. Thus, maximum spur amplitude in (1) occurs when .

(ii)We have arbitrarily assumed a phase relationship between ref and dco, given the uncertainty of the TDC quantization. Therefore, in our example, a favorable time delay between dco and ref exists which prevents to fall into the holes of the characteristic in Figure 8(b) and to generate glitches.

(iii)When is finer than the TDC resolution (which is the common situation), the phase relationship between ref and dco changes. Thus, the condition in (ii) may periodically occur. As a consequence, the and sequences show some missing glitches, thus slightly altering the result in (1).

## 6. Glitch-Correction Logic

A possible countermeasure to the glitch problem presented in the previous section has been already proposed in [11]. In that work, the derivative of is monitored, and if its magnitude is higher than 0.5, is decreased/increased by 1. In this way, the glitch in Figure 8 is removed. However, this solution has the disadvantage of altering the transient behavior. If a large variation in the DCO frequency occurs, which causes a step of +1 (or more) in the value, the loop would not be able to track the frequency, unless the corrector is disabled. In the case of an unexpected frequency step, that may seriously affect the lock behavior.

(a)If the integer frequency error differs from 0 or 1, then the loop is considered to be out of lock and no correction is applied. Thus, is simply given by and is not varied.

(b)In timestamp in the example in Figure 8(a), is not incremented with respect to , while the TDC overflows. Therefore, and . Assuming , the value of is , thus canceling the glitch, and is decremented by 1.

(c)In timestamp , is incremented with respect to , while the TDC does not overflow. Therefore, and . If this situation occurs after (b), the flag . Thus, the algorithm sets to , canceling again the glitch, and is incremented by 1, returning to zero.

It is easy to check that if a sudden change in the DCO frequency causes a step of +1 in , thanks to the adoption of the flag , this circuit removes only the first sample +1 of . Then, it leaves the loop operating normally.

The case in which
is not reported here, for the sake of brevity. In that case, the algorithm applies a correction when
and the TDC underflows and when
and the TDC does not underflow. The signs of the corrections of
and *F* are swapped with respect to the case in Figure 9.

## 7. Simulations Results

The AD-PLL is simulated by adding a phase noise to the DCO signal of dBc/Hz at 1 MHz offset from the carrier. The fractional FCW word is set to (95 + 1/16 + 351/ ) and the reference frequency is 40 MHz. Therefore, the output frequency is 3.8025 GHz. The time skew between counter and TDC is assumed to be about = 15 ps, which is slightly less than one TDC LSB.

## 8. Conclusions

The design of an AD-PLL for the 3.3–3.8 WiMAX bandwidth has been presented. The main focus of this work is the design of the TDC, which sets the in-band noise performance of the synthesizer and, above all, it may be an important source of spurious tone. To fully exploit the digital-intensive approach, the TDC is implemented as a bang-bang DLL and it designed to guarantee the required time resolution. However, the unavoidable time skew between the counter and the TDC inputs in the AD-PLL is demonstrated to be responsible of generating glitches at the PLL comparison node and in turn large spurs in the PLL output spectrum. A digital glitch corrector has been presented which solves this impairment and it is able to work correctly even during a lock transient.

## Declarations

### Acknowledgment

This work was partially supported by the Communication Integration Research Lab of Intel Corp., Hillsboro OR.

## Authors’ Affiliations

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