The presence of a time skew between the counter and the TDC inputs is almost unavoidable. However, it causes an error in the feedback signal. Note that the phenomenon highlighted in this section is general and it does not depend on our particular TDC implementation. We consider a delay applied to the counter input, as shown in Figure 7. In this situation, the counter will be driven by the delayed DCO signal, indicated as dco, while the TDC input is the original DCO signal, that is, dco in Figure 7. Now, the instant in which the TDC overflows (or underflows) and that in which the counter increments (or reduces) its steady-state output does not coincide.

To illustrate this behavior, we consider again the example discussed in Section 2. The waveforms resulting from the application of are sketched in Figure 8(a). Because of the skew, the counter output increments by 3 in the following reference period with respect to Figure 2. Instead, the TDC output is unperturbed. In this figure, the time skew has been assumed to be equal to , but the same and graphs would have been obtained for . The net result of the time shift of the sequence is the generation of a periodic bipolar glitch (with frequency ) in the error signal . The average value of is zero; therefore the loop does not respond; however, this periodic disturbances produces spurious tones at the output. The signal , which is given by the accumulation of and is proportional to the phase error, will be a periodic square-wave with duty cycle .

The same impairment can be visualized by combining again the TDC and the counter conversion characteristics as shown in Figure 8(b). The effect of the positive time skew is the generation of holes in the characteristic. At steady state, this staircase is swept, going up from one step to another one. Therefore, depending on the initial phase, the converter input may periodically fall into the holes. The resulting phase error is as large as one LSB of the coarse converter, that is, of the counter.

Evaluating the fundamental frequency and the amplitude of the spur in the previous example is particularly simple. Assuming that the spur fundamental falls out of the PLL band, can be calculated following [10]. Thus,

with being the frequency response magnitude of the loop filter and being the DCO frequency resolution.

The example presented here is particularly simple, for the sake of clarity. In particular, the TDC has enough resolution to detect the fractional part of FCW, which makes this case similar to what happens in a standard PLL with an integer division factor. In other cases, the behavior may be slightly more complex; the main issues to be considered are listed as follows:

(i)If is larger than (in our example), the counter sequence will be shifted with respect to the TDC sequence by more than one reference cycle. So, the sequence will include some 0 s between +1 and –1 and its integral will be a sequence of pulses, whose duty cycle depends on the number of 0 s in the sequence. Thus, maximum spur amplitude in (1) occurs when .

(ii)We have arbitrarily assumed a phase relationship between ref and dco, given the uncertainty of the TDC quantization. Therefore, in our example, a favorable time delay between dco and ref exists which prevents to fall into the holes of the characteristic in Figure 8(b) and to generate glitches.

(iii)When is finer than the TDC resolution (which is the common situation), the phase relationship between ref and dco changes. Thus, the condition in (ii) may periodically occur. As a consequence, the and sequences show some missing glitches, thus slightly altering the result in (1).