Skip to main content
  • Research Article
  • Open access
  • Published:

A Predictive NoC Architecture for Vision Systems Dedicated to Image Analysis

Abstract

The aim of this paper is to describe an adaptive and predictive FPGA embedded architecture for vision systems dedicated to image analysis. A large panel of image analysis algorithms with some common characteristics must be mapped onto this architecture. Major characteristics of such algorithms are extracted to define the architecture. This architecture must easily adapt its structure to algorithm modifications. According to required modifications, few parts must be either changed or adapted. An NoC approach is used to break the hardware resources down as stand-alone blocks and to improve predictability and reuse aspects. Moreover, this architecture is designed using a globally asynchronous locally synchronous approach so that each local part can be optimized separately to run at its best frequency. Timing and resource prediction models are presented. With these models, the designer defines and evaluates the appropriate structure before the implementation process. The implementation of a particle image velocimetry algorithm illustrates this adaptation. Experimental results and predicted results are close enough to validate our prediction models for PIV algorithms.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31]

References

  1. Keating M, Bricaud P: Reuse Methodology Manual for System-on-Chip Designs. Kluwer Academic, Boston, Mass, USA; 1998.

    Book  Google Scholar 

  2. Benini L, De Micheli G: Networks on chips: a new SoC paradigm. Computer 2002,35(1):70-78. 10.1109/2.976921

    Article  Google Scholar 

  3. Jantsch A, Tenhunen H: Networks on Chip. Kluwer Academic, Boston, Mass, USA; 2003.

    Book  Google Scholar 

  4. Dally WJ, Towles B: Route packets, not wires: on-chip interconnection networks. Proceedings of the 38th Design Automation Conference (DAC '01), June 2001, Las Vegas, Nev, USA 684-689.

    Google Scholar 

  5. Xu J, Wolf W, Henkel J, Chakradhar S: A design methodology for application-specific Networks on Chip. ACM Transactions on Embedded Computing Systems 2006,5(2):263-280. 10.1145/1151074.1151076

    Article  Google Scholar 

  6. Millberg M, Nilsson E, Thid R, Kumar S, Jantsch A: The Nostrum backbone-a communication protocol stack for networks on chip. Proceedings of the 17th International Conference on VLSI Design (ICVD '04), January 2004, Mumbai, India 17: 693-696.

    Article  Google Scholar 

  7. Forsell M: A scalable high-performance computing solution for networks on chips. IEEE Micro 2002,22(5):46-55. 10.1109/MM.2002.1044299

    Article  Google Scholar 

  8. Liang J, Swaminathan S, Tessier R: ASOC: a scalable, single-chip communications architecture. Proceedings of International Conference on Parallel Architectures and Compilation Techniques (PACT '00), October 2000, Philadelphia, Pa, USA 37-46.

    Google Scholar 

  9. Taylor MB, Kim J, Miller J, et al.: The raw microprocessor: a computational fabric for software circuits and general-purpose programs. IEEE Micro 2002,22(2):25-35. 10.1109/MM.2002.997877

    Article  Google Scholar 

  10. Zeferino CA, Susin AA: SoCIN: a parametric and scalable network-on-chip. Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI '03), September 2003, Sao Paulo, Brazil

    Google Scholar 

  11. Adriahantenaina A, Charlery H, Greiner A, Mortiez L, Zeferino CA: SPIN: a scalable, packet switched, on-chip micro-network. Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '03), March 2003, Munich, Germany

    Google Scholar 

  12. Karim F, Nguyen A, Dey S: An interconnect architecture for networking systems on chips. IEEE Micro 2002,22(5):36-45. 10.1109/MM.2002.1044298

    Article  Google Scholar 

  13. Siguenza-Tortosa D, Nurmi J: Proteo: a new approach to network-on-chip. Proceedings of International Conference on Communication Systems and Networks (CSN '02), September 2002, Malaga, Spain

    Google Scholar 

  14. Seul M, O'Gorman L, Sammon MJ: Practical Algorithms for Image Analysis: Descriptions, Examples, and Code. Press Syndicate of the University of Cambridge, Cambridge, UK; 2000.

    Google Scholar 

  15. Sutherland K, Ironside JW: Novel application of image analysis to the detection of spongiform change. Analytical and Quantitative Cytology and Histology 1994,16(6):430-434.

    Google Scholar 

  16. Campobello G, Castano M, Ciofi C, Mangano D: GALS networks on chip: a new solution for asynchronous delay-insensitive links. Proceedings of the Conference on Design, Automation and Test in Europe (DATE '06) , March 2006, Munich, Germany 160-165.

    Google Scholar 

  17. Hemani A, Jantsch A: Network on chip: an architecture for billion transistor era. Proceedings of the 18th NorChip Conference, November 2000, Turku, Finland 166-173.

    Google Scholar 

  18. Siegmund R, Müller D: Efficient modeling and synthesis of on-chip communication protocols for network-on-chip design. Proceedings of the International Symposium on Circuits and Systems (ISCAS '03), May 2003, Bangkok, Thailand 5: 81-84.

    Google Scholar 

  19. Hemani A, Meincke T, Kumar S, et al.: Lowering power consumption in clock by using globally asynchronous locally synchronous design style. Proceedings of the 36th ACM/IEEE Conference on Design Automation (DAC '99), June 1999, New Orleans, La, USA 873-878.

    Google Scholar 

  20. Muttersbach J, Villiger T, Fichtner W: Practical design of globally-asynchronous locally synchronous systems. Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '00), April 2000, Eilat, Israel 52-59.

    Chapter  Google Scholar 

  21. Muttersbach J: Globally-asynchronous locally-synchronous architectures for VLSI systems, Ph.D. thesis. ETH, Zürich, Germany; 2001.

    Google Scholar 

  22. Bhunia S, Datta A, Banerjee N, Roy K: GAARP: a power-aware GALS architecture for real-time algorithm-specific tasks. IEEE Transactions on Computers 2005,54(6):752-766. 10.1109/TC.2005.99

    Article  Google Scholar 

  23. Brunvand E: Implementing self-timed systems with FPGAs. In FPGAs. Edited by: Moore W, Luk W. Abingdon EE&CS Books, Abingdon, England; 1991:312-323.

    Google Scholar 

  24. Erickson K: Asynchronous FPGA risks. Proceedings of the 4th Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD '00), September 2000, Laurel, Md, USA

    Google Scholar 

  25. Aubert A, Bochard N, Fresse V: An adaptive embedded architecture for real-time PIV algorithms. Proceedings of the 14th European Signal Processing Conference (EUSIPCO '06), September 2006, Florence, Italy

    Google Scholar 

  26. Adrian RJ: Particle image techniques for experimental fluid mechanics. Annual Review of Fluid Mechanics 1991, 23: 261-304. 10.1146/annurev.fl.23.010191.001401

    Article  Google Scholar 

  27. Keane RK, Adrian RJ: Theory of cross-correlation analysis of PIV images. Applied Scientific Research 1992,49(3):191-215. 10.1007/BF00384623

    Article  Google Scholar 

  28. Altera Corp : Altera Stratix II EP2S60 NIOS II Development board. datasheet, 2004, http://www.altera.com

  29. Leeser M, Miller S, Haiqian Y: Smart camera based on reconfigurable hardware enables diverse real-time applications. Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '04), April 2004, Napa, Calif, USA 147-155.

    Chapter  Google Scholar 

  30. Schiwietz T, Westerman R: GPU-PIV. Proceedings of the Vision, Modeling, and Visualization Conference (VMV '04), November 2004, Stanford, Calif, USA 151-158.

    Google Scholar 

  31. Fujiwara T, Fujimoto K, Maruyama T: A real-time visualization system for PIV. Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL '03), September 2003, Lisbon, Portugal, Lecture Notes in Computer Science 2778: 437-447.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Virginie Fresse.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and permissions

About this article

Cite this article

Fresse, V., Aubert, A. & Bochard, N. A Predictive NoC Architecture for Vision Systems Dedicated to Image Analysis. J Embedded Systems 2007, 097929 (2007). https://doi.org/10.1155/2007/97929

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1155/2007/97929

Keywords