Open Access

A Shared Memory Module for Asynchronous Arrays of Processors

EURASIP Journal on Embedded Systems20072007:086273

Received: 1 August 2006

Accepted: 1 March 2007

Published: 9 May 2007


A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μ m CMOS.


High ThroughputControl StructureShared MemoryMemory LoadElectronic Circuit

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Authors’ Affiliations

Department of Electrical and Computer Engineering, University of California, Davis, USA


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© Meeuwsen et al. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.