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A Shared Memory Module for Asynchronous Arrays of Processors

EURASIP Journal on Embedded Systems volume 2007, Article number: 086273 (2007) Cite this article

Abstract

A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μ m CMOS.

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Author information

Affiliations

  1. Department of Electrical and Computer Engineering, University of California, Davis, CA, 95616-5294, USA

    Michael J Meeuwsen, Zhiyi Yu & Bevan M Baas

Authors
  1. Michael J Meeuwsen
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  2. Zhiyi Yu
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  3. Bevan M Baas
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Corresponding author

Correspondence to Michael J Meeuwsen.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Meeuwsen, M.J., Yu, Z. & Baas, B.M. A Shared Memory Module for Asynchronous Arrays of Processors. J Embedded Systems 2007, 086273 (2007). https://doi.org/10.1155/2007/86273

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Keywords

  • High Throughput
  • Control Structure
  • Shared Memory
  • Memory Load
  • Electronic Circuit
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