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A High-End Real-Time Digital Film Processing Reconfigurable Platform

Abstract

Digital film processing is characterized by a resolution of at least 2 K (2048×1536 pixels per frame at 30 bit/pixel and 24 pictures/s, data rate of 2.2 Gbit/s); higher resolutions of 4 K (8.8 Gbit/s) and even 8 K (35.2 Gbit/s) are on their way. Real-time processing at this data rate is beyond the scope of today's standard and DSP processors, and ASICs are not economically viable due to the small market volume. Therefore, an FPGA-based approach was followed in the FlexFilm project. Different applications are supported on a single hardware platform by using different FPGA configurations. The multiboard, multi-FPGA hardware/software architecture, is based on Xilinx Virtex-II Pro FPGAs which contain the reconfigurable image stream processing data path, large SDRAM memories for multiple frame storage, and a PCI-Express communication backbone network. The FPGA-embedded CPU is used for control and less computation intensive tasks. This paper will focus on three key aspects: (a) the used design methodology which combines macro component configuration and macrolevel floorplaning with weak programmability using distributed microcoding, (b) the global communication framework with communication scheduling, and (c) the configurable multistream scheduling SDRAM controller with QoS support by access prioritization and traffic shaping. As an example, a complex noise reduction algorithm including a 2.5-dimension discrete wavelet transformation (DWT) and a full 16×16 motion estimation (ME) at 24 fps, requiring a total of 203 Gops/s net computing performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth, will be shown.

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References

  1. Quantel, http://www.quantel.com/

  2. Discreet, http://www.discreet.com/

  3. FlexFilm, http://www.flexfilm.org/

  4. do Carmo Lucas A, Ernst R: An image processor for digital film. Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '05), July 2005, Samos, Greece 219-224.

    Google Scholar 

  5. do Carmo Lucas A, Heithecker S, Rüfer P, et al.: A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications. Proceedings of the Conference on Design, Automation and Test in Europe (DATE '06), March 2006, Munich, Germany 1: 194-199.

    Google Scholar 

  6. Xilinx, http://www.xilinx.com/

  7. PCI-SIG, PCI-Express Base Specification Revision 1.0, July 2002

  8. PCI-SIG, http://www.pcisig.com/

  9. IEC 60027-2: Letter symbols to be used in electrical technology—part 2: telecommunications and electronics. IEC, 3.0 edition, August 2005

  10. Dutta S, Jensen R, Rieckmann A: Viper: a multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Design and Test of Computers 2001,18(5):21-31. 10.1109/54.953269

    Article  Google Scholar 

  11. Ahn JH, Dally WJ, Khailany B, Kapasi UJ, Das A: Evaluating the imagine stream architecture. ACM SIGARCH Computer Architecture News 2004,32(2):14. 10.1145/1028176.1006734

    Article  Google Scholar 

  12. Hunt Engineering, http://www.hunteng.co.uk/

  13. Nallatech, http://www.nallatech.com/

  14. SGI, http://www.sgi.com/products/rasc/

  15. Park J, Diniz PC: Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines. Proceedings of the 14th International Symposium on System Synthesis (ISSS '01), September-October 2001, Montreal, Quebec, Canada 221-226.

    Google Scholar 

  16. Oxford Micro Devices, http://www.omdi.com/

  17. Texas Instruments, http://www.ti.com/

  18. Analog Devices, http://www.analog.com/

  19. Strzodka R, Garbe C: Real-time motion estimation and visualization on graphics cards. Proceedings of the 15th IEEE Visualization Conference (VIS '04), October 2004, Austin, Tex, USA 545-552.

    Google Scholar 

  20. Kahle JA, Day MN, Hofstee HP, Johns CR, Maeurer TR, Shippy D: Introduction to the cell multiprocessor. IBM Journal of Research and Development 2005,49(4-5):589-604. 10.1147/rd.494.0589

    Article  Google Scholar 

  21. Panda PR, Catthoor F, Dutt ND, et al.: Data and memory optimization techniques for embedded systems. ACM Transactions on Design Automation of Electronic Systems 2001,6(2):149-206. 10.1145/375977.375978

    Article  Google Scholar 

  22. Cuppu V, Jacob B, Davis B, Mudge T: High-performance DRAMs in workstation environments. IEEE Transactions on Computers 2001,50(11):1133-1153. 10.1109/12.966491

    Article  Google Scholar 

  23. Cuppu V, Jacob B, Davis B, Mudge T: A performance comparison of contemporary DRAM architectures. Proceedings of the 26th International Symposium on Computer Architecture (ISCA '99), May 1999, Atlanta, Ga, USA 222-233.

    Google Scholar 

  24. Rixner S, Dally WJ, Kapasi UJ, Mattson P, Owens JD: Memory access scheduling. Proceedings of the 27th International Symposium on Computer Architecture (ISCA '00), June 2000, Vancouver, BC, Canada 128-138.

    Google Scholar 

  25. Heithecker S, do Carmo Lucas A, Ernst R: A mixed QoS SDRAM controller for FPGA-based high-end image processing. Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS '03), August 2003, Seoul, Korea 322-327.

    Google Scholar 

  26. Heithecker S, Ernst R: Traffic shaping for an FPGA-based SDRAM controller with complex QoS requirements. Proceedings of the 42nd Design Automation Conference (DAC '05), 2005, Anaheim, Calif, USA 575-578.

  27. Weber M: Arbiters: design ideas and coding styles. In Synopsys Users Group (SNUG), Boston, Mass, USA, 2001. http://www.snug-universal.org/cgi-bin/search/search.cgi?Boston,+2001 In Synopsys Users Group (SNUG), Boston, Mass, USA, 2001.

  28. Lee K-B, Lin T-C, Jen C-W: An efficient quality-aware memory controller for multimedia platform SOC. IEEE Transactions on Circuits and Systems for Video Technology 2005,15(5):620-633. 10.1109/TCSVT.2005.846412

    Article  Google Scholar 

  29. Sonics, Sonics MemMax 2.0 Multi-threaded DRAM Access Scheduler, Data sheet, Sonics, 2005. http://www.sonicsinc.com/

  30. Weber W-D: Efficient Shared DRAM Subsystems for SOCs. In Microprocessor Forum, 2001

  31. Macián C, Dharmapurikar S, Lockwood J: Beyond performance: secure and fair memory management for multiple systems on a chip. Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT '03), December 2003, Tokyo, Japan 348-351.

    Google Scholar 

  32. Goossens K, Gangwal OP, Röver J, Niranjan AP: Interconnect and memory organization in SOCs for advanced set-top boxes and TV. In Interconnect-Centric Design for Advanced SOC and NOC. Springer, New York, NY, USA; 2004. chapter 16

    Google Scholar 

  33. Harmsze F, Timmer A, van Meerbergen J: Memory arbitration and cache management in stream-based systems. Proceedings of the Conference on Design, Automation and Test in Europe (DATE '00), March 2000, Paris, France 257-262.

    Chapter  Google Scholar 

  34. ARM. PrimeCell Dynamic Memory Controller (PL340). ARM, 2005

  35. Xilinx, Xilinx Memory Solutions, http://www.xilinx.com/products/design_resources/mem_corner/index.htm

  36. Henriss K, Rüffer P, Ernst R: A reconfigurable hardware platform for digital real-time signal processing in television studios. Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '00), April 2000, Napa Valley, Calif, USA 285.

    Google Scholar 

  37. Eichner S, Scheller G, Wessely U, Rückert H, Hedtke R: Motion compensated spatial-temporal reduction of film grain noise in the wavelet domain. Proceedings of the Society of Motion Picture and Television Engineers Technical Conference (SMPTE '05), November 2005, New York, NY, USA

    Google Scholar 

  38. Sanz C, Garrido MJ, Meneses JM: VLSI architecture for motion estimation using the block-matching algorithm. Proceedings of the European conference on Design and Test (EDTC '96), March 1996, Paris, France 310-314.

    Chapter  Google Scholar 

  39. Rout S: Orthogonal vs. biorthogonal wavelets for image compression, M.S. thesis. Virginia Polytechnic Institute and State University, Blacksburg, Va, USA; 2003.

    Google Scholar 

  40. Zervas ND, Anagnostopoulos GP, Spiliotopoulos V, Andreopoulos Y, Goutis CE: Evaluation of design alternatives for the 2-D-discrete wavelet transform. IEEE Transactions on Circuits and Systems for Video Technology 2001,11(12):1246-1262. 10.1109/76.974679

    Article  Google Scholar 

  41. Brislawn CM: Classification of nonexpansive symmetric extension transforms for multirate filter banks. Applied and Computational Harmonic Analysis 1996,3(4):337-357. 10.1006/acha.1996.0026

    MATH  Article  Google Scholar 

  42. Guthaus MR, Ringenberg JS, Ernst D, Austin TM, Mudge T, Brown RB: MiBench: a free, commercially representative embedded benchmark suite. Proceedings of the 4th Annual IEEE International Workshop on Workload Characterization (WWC-4'01), December 2001, Austin, Tex, USA 3-14.

    Chapter  Google Scholar 

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Correspondence to Sven Heithecker.

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Heithecker, S., do Carmo Lucas, A. & Ernst, R. A High-End Real-Time Digital Film Processing Reconfigurable Platform. J Embedded Systems 2007, 085318 (2007). https://doi.org/10.1155/2007/85318

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Keywords

  • Discrete Wavelet Transformation
  • Processing Reconfigurable
  • Noise Reduction Algorithm
  • Communication Schedule
  • Frame Memory