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EURASIP Journal on Embedded Systems
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  • Research Article
  • Open Access

A High-End Real-Time Digital Film Processing Reconfigurable Platform

EURASIP Journal on Embedded Systems20072007:085318

https://doi.org/10.1155/2007/85318

©  Heithecker et al. 2007

  • Received: 15 May 2006
  • Accepted: 22 December 2006
  • Published:

Abstract

Digital film processing is characterized by a resolution of at least 2 K (2048×1536 pixels per frame at 30 bit/pixel and 24 pictures/s, data rate of 2.2 Gbit/s); higher resolutions of 4 K (8.8 Gbit/s) and even 8 K (35.2 Gbit/s) are on their way. Real-time processing at this data rate is beyond the scope of today's standard and DSP processors, and ASICs are not economically viable due to the small market volume. Therefore, an FPGA-based approach was followed in the FlexFilm project. Different applications are supported on a single hardware platform by using different FPGA configurations. The multiboard, multi-FPGA hardware/software architecture, is based on Xilinx Virtex-II Pro FPGAs which contain the reconfigurable image stream processing data path, large SDRAM memories for multiple frame storage, and a PCI-Express communication backbone network. The FPGA-embedded CPU is used for control and less computation intensive tasks. This paper will focus on three key aspects: (a) the used design methodology which combines macro component configuration and macrolevel floorplaning with weak programmability using distributed microcoding, (b) the global communication framework with communication scheduling, and (c) the configurable multistream scheduling SDRAM controller with QoS support by access prioritization and traffic shaping. As an example, a complex noise reduction algorithm including a 2.5-dimension discrete wavelet transformation (DWT) and a full 16×16 motion estimation (ME) at 24 fps, requiring a total of 203 Gops/s net computing performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth, will be shown.

Keywords

  • Discrete Wavelet Transformation
  • Processing Reconfigurable
  • Noise Reduction Algorithm
  • Communication Schedule
  • Frame Memory

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Authors’ Affiliations

(1)
Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, Braunschweig, 38106, Germany

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Copyright

© Heithecker et al. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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