EURASIP Journal on Embedded Systems

EURASIP Journal on Embedded Systems Cover Image
Research Article
Open Access

A Framework for System-Level Modeling and Simulation of Embedded Systems Architectures

  • Cagkan Erbas1Email author,
  • Andy D Pimentel1,
  • Mark Thompson1 and
  • Simon Polstra1
EURASIP Journal on Embedded Systems20072007:082123

https://doi.org/10.1155/2007/82123

©  Erbas et al. 2007

Received: 31 May 2006

Accepted: 18 June 2007

Published: 29 July 2007

Abstract

The high complexity of modern embedded systems impels designers of such systems to model and simulate system components and their interactions in the early design stages. It is therefore essential to develop good tools for exploring a wide range of design choices at these early stages, where the design space is very large. This paper provides an overview of our system-level modeling and simulation environment, Sesame, which aims at efficient design space exploration of embedded multimedia system architectures. Taking Sesame as a basis, we discuss many important key concepts in early systems evaluation, such as Y-chart-based systems modeling, design space pruning and exploration, trace-driven cosimulation, and model calibration.

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Authors’ Affiliations

(1)
Computer Systems Architecture Group, Informatics Institute, Faculty of Science, University of Amsterdam

References

  1. Keutzer K, Newton AR, Rabaey JM, Sangiovanni-Vincentelli A: System-level design: orthogonalization of concerns and platform-based design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2000,19(12):1523-1543. 10.1109/43.898830View ArticleGoogle Scholar
  2. Pimentel AD, Erbas C, Polstra S: A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Transactions on Computers 2006,55(2):99-112. 10.1109/TC.2006.16View ArticleGoogle Scholar
  3. Bakshi A, Prasanna V, Ledeczi A: Milan: a model based integrated simulation framework for design of embedded systems. Proceedings of the Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES '01), June 2001, Snowbird, Utah, USA 82-87.View ArticleGoogle Scholar
  4. Balarin F, Watanabe Y, Hsieh H, Lavagno L, Passerone C, Sangiovanni-Vincentelli A: Metropolis: an integrated electronic system design environment. Computer 2003,36(4):45-52. 10.1109/MC.2003.1193228View ArticleGoogle Scholar
  5. Cassidy A, Paul J, Thomas D: Layered, multi-threaded, high-level performance design. Proceedings of the International Conference on Design, Automation and Test in Europe (DATE '03), March 2003, Munich, Germany 954-959.Google Scholar
  6. Balarin F, Giusto PD, Jurecska A, et al.: Hardware-Software Co-Design of Embedded Systems: The POLIS Approach. Kluwer Academic, Boston, Mass, USA; 1997.MATHView ArticleGoogle Scholar
  7. Kienhuis B, Deprettere E, Vissers K, van der Wolf P: An approach for quantitative analysis of application-specific dataflow architectures. Proceedings of IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP '97), July 1997, Zurich, Switzerland 338-349.View ArticleGoogle Scholar
  8. Kahn G: The semantics of a simple language for parallel programming. Proceedings of the IFIP Congress on Information Processing, August 1974, Stockholm, Sweden 471-475.Google Scholar
  9. Verdoolaege S, Nikolov H, Stefanov T: Improved derivation of process networks. Proceedings of the 4th International Workshop on Optimization for DSP and Embedded Systems (ODES '06), March 2006, New York, NY, USA Google Scholar
  10. Stefanov T, Kienhuis B, Deprettere E: Algorithmic transformation techniques for efficient exploration of alternative application instances. Proceedings of the 10th International Symposium on Hardware/Software Codesign (CODES '02), May 2002, Estes Park, Colo, USA 7-12.Google Scholar
  11. Erbas C, Pimentel AD: Utilizing synthesis methods in accurate system-level exploration of heterogeneous embedded systems. Proceedings of IEEE Workshop on Signal Processing Systems (SIPS '03), August 2003, Seoul, Korea 310-315.Google Scholar
  12. Erbas C, Cerav-Erbas S, Pimentel AD: Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design. IEEE Transactions on Evolutionary Computation 2006,10(3):358-374. 10.1109/TEVC.2005.860766View ArticleGoogle Scholar
  13. Erbas C, Cerav-Erbas S, Pimentel AD: A multiobjective optimization model for exploring multiprocessor mappings of process networks. Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, October 2003, Newport Beach, Calif, USA 182-187.Google Scholar
  14. Zitzler E, Laumanns M, Thiele L: SPEA2: improving the strength pareto evolutionary algorithm for multiobjective optimization. In Evolutionary Methods for Design, Optimisation and Control with Application to Industrial Problems. Edited by: Giannakoglou K, Tsahalis D, Periaux J, Papailiou KD, Fogarty T. International Center for Numerical Methods in Engineering, Barcelona, Spain; 2002:95-100.Google Scholar
  15. de Kock EA, Essink G, Smits W, et al.: YAPI: application modeling for signal processing systems. Proceedings of the 37th Design Automation Conference (DAC '00), June 2000, Los Angeles, Calif, USA 402-405.Google Scholar
  16. Coffland JE, Pimentel AD: A software framework for efficient system-level performance evaluation of embedded systems. Proceedings of the ACM Symposium on Applied Computing, March 2003, Melbourne, Fla, USA 666-671.Google Scholar
  17. Thompson M, Pimentel AD: A high-level programming paradigm for systemC. In Proceedings of the 4th International Workshops on Systems, Architectures, Modeling, and Simulation (SAMOS '04), July 2004, Samos, Greece, Lecture Notes in Computer Science. Volume 3133. Springer; 530-539.View ArticleGoogle Scholar
  18. Thompson M, Pimentel AD, Polstra S, Erbas C: A mixed-level co-simulation method for system-level design space exploration. Proceedings of the IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia, October 2006, Seoul, Korea 27-32.Google Scholar
  19. Kienhuis B, Rijpkema E, Deprettere E: Compaan: deriving process networks from Matlab for embedded signal processing architectures. Proceedings of the 18th International Workshop Hardware/Software Codesign (CODES '00), May 2000, San Diego, Calif, USA 13-17.Google Scholar
  20. Zissulescu C, Stefanov T, Kienhuis B, Deprettere E: Laura: leiden architecture research and exploration tool. In Proceedings of the 13th International Conference on Field-Programmable Logic and Applications (FPL '03), September 2003, Lisbon, Portugal, Lecture Notes in Computer Science. Volume 2778. Edited by: Cheung P, Constantinides G, de Sousa J. Springer; 911-920.Google Scholar
  21. Pimentel AD, Terpstra F, Polstra S, Coffland JE: On the modeling of intra-task parallelism in task-level parallel embedded systems. In Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation. Edited by: Bhattacharyya S, Deprettere E, Teich J. Springer, Berlin, Germany; 2003:85-105.Google Scholar
  22. Pimentel AD: The artemis workbench for system-level performance evaluation of embedded systems. International Journal of Embedded Systems 2005.,1(7):Google Scholar
  23. Mihal A, Kulkarni C, Sauer C, et al.: Developing architectural platforms: a disciplined approach. IEEE Design and Test of Computers 2002,19(6):6-16. 10.1109/MDT.2002.1047739View ArticleGoogle Scholar
  24. Mohanty S, Prasanna VK: Rapid system-level performance evaluation and optimization for application mapping onto SoC architectures. Proceedings of the 15th Annual IEEE International ASIC/SOC Conference, September 2002, Rochester, NY, USA 160-167.View ArticleGoogle Scholar
  25. Kogel T, Wieferin A, Leupers R, et al.: Virtual architecture mapping: a systemC based methodology for architectural exploration of system-on-chip designs. Proceedings of the 3rd International Workshop on Computer Systems: Architectures, Modeling, and Simulation (SAMOS '03), July 2003, Samos, Greece 138-148.Google Scholar
  26. Gries M: Methods for evaluating and covering the design space during early design development. Integration, the VLSI Journal 2004,38(2):131-183. 10.1016/S0167-9260(04)00032-XView ArticleGoogle Scholar
  27. Lahiri K, Raghunathan A, Dey S: System-level performance analysis for designing on-chip communication architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2001,20(6):768-783. 10.1109/43.924830View ArticleGoogle Scholar
  28. Zivkovic V, Deprettere E, van der Wolf P, de Kock E: Fast and accurate multiprocessor architecture exploration with symbolic programs. Proceedings of the International Conference on Design, Automation and Test in Europe (DATE '03), March 2003, Munich, Germany 656-661.Google Scholar
  29. Lieverse P, van der Wolf P, Deprettere E, Vissers K: A methodology for architecture exploration of heterogeneous signal processing systems. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 2001,29(3):197-207.MATHView ArticleGoogle Scholar
  30. Brooks D, Tiwari V, Martonosi M: Wattch: a framework for architectural-level power analysis and optimizations. Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA '00), June 2000, Vancouver, BC, Canada 83-94.Google Scholar
  31. Ye W, Vijaykrishnan N, Kandemir M, Irwin MJ: The design and use of simplepower: a cycle-accurate energy estimation tool. Proceedings of the 37th Design Automation Conference (DAC '00), June 2000, Los Angeles, Calif, USA 340-345.View ArticleGoogle Scholar

Copyright

© Erbas et al. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.