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pn: A Tool for Improved Derivation of Process Networks

EURASIP Journal on Embedded Systems volume 2007, Article number: 075947 (2007) Cite this article

Abstract

Current emerging embedded System-on-Chip platforms are increasingly becoming multiprocessor architectures. System designers experience significant difficulties in programming these platforms. The applications are typically specified as sequential programs that do not reveal the available parallelism in an application, thereby hindering the efficient mapping of an application onto a parallel multiprocessor platform. In this paper, we present our compiler techniques for facilitating the migration from a sequential application specification to a parallel application specification using the process network model of computation. Our work is inspired by a previous research project called Compaan. With our techniques we address optimization issues such as the generation of process networks with simplified topology and communication without sacrificing the process networks' performance. Moreover, we describe a technique for compile-time memory requirement estimation which we consider as an important contribution of this paper. We demonstrate the usefulness of our techniques on several examples.

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Authors and Affiliations

  1. Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Niels Bohrweg 1, CA, Leiden, 2333, The Netherlands

    Sven Verdoolaege, Hristo Nikolov & Todor Stefanov

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  1. Sven Verdoolaege
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  2. Hristo Nikolov
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  3. Todor Stefanov
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Correspondence to Sven Verdoolaege.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Verdoolaege, S., Nikolov, H. & Stefanov, T. pn: A Tool for Improved Derivation of Process Networks. J Embedded Systems 2007, 075947 (2007). https://doi.org/10.1155/2007/75947

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