Skip to main content

Advertisement

Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems

Article metrics

  • 769 Accesses

  • 1 Citations

Abstract

This paper presents a tool for automatic generation of the memory management implementation for spatial and temporal real-time video processing systems targeting field programmable gate arrays (FPGAs). The generator creates all the necessary memory and control functionality for a functional spatio-temporal video processing system. The required memory architecture is automatically optimized and mapped to the FPGAs' memory resources thus producing an efficient implementation in terms of used internal resources. The results in this paper show that the tool is able to efficiently and automatically generate all required memory management modules for both spatial and temporal real-time video processing systems.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28]

References

  1. 1.

    Bramberger M, Doblander A, Maier A, Rinner B, Schwabach H: Distributed embedded smart cameras for surveillance applications. Computer 2006,39(2):68-75. 10.1109/MC.2006.55

  2. 2.

    do Carmo Lucas A, Heithecker S, Ruffer P, et al.: A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications. Proceedings of Design, Automation and Test in Europe (DATE '06), March 2006, Munich, Germany 1: 1-6.

  3. 3.

    http://www.mathworks.com/products/simulink/

  4. 4.

    System-C Language Reference Manual http://www.systemc.org

  5. 5.

    Green P, Edwards M, Essa S: UML for system-level design: extending the object model for systems-on-chips. In System on Chip Design Languages. Edited by: Mignotte A, Villar E, Horobin L. Kluwer Academic, Boston, Mass, USA; 2002.

  6. 6.

    Verhaegh WFJ, Lippens PER, Aarts EHL, Korst JHM, van Meerbergen JL, van der Werf A: Modelling periodicity by PHIDEO streams. Proceedings of 6th International Workshop on High Level Synthesis, November 1992, Dana Point, Calif, USA 256-266.

  7. 7.

    Gajski DD, Vahid F, Narayan S, Gong J: Specification and Design of Embedded Systems. Prentice-Hall, Englewood Cliffs, NJ, USA; 1994.

  8. 8.

    Thörnberg B, Norell H, O'Nils M: Conceptual interface and memory-modeling for real time image processing systems, IMEM, a tool for modeling, simulation, and design parameter extraction. Proceedings of IEEE Workshop on Multimedia Signal Processing (MMSP '02), December 2002, St.Thomas, Virgin Islands, USA

  9. 9.

    Catthoor F, Wuytack S, De Greef E, Balasa F, Nachtergaele L, Vandecappelle A: Custom Memory Management Methodology. Kluwer Academic, Boston, Mass, USA; 1998.

  10. 10.

    Thörnberg B, Norell H, O'Nils M: IMEM: an object-oriented memory- and interface modelling approach for real-time video processing systems. Proceedings of the Forum on Specification and Design Languages, September 2002, Marseille, France

  11. 11.

    Panda PR: SystemC - a modeling platform supporting multiple design abstractions. Proceedings of the 14th International Symposium on System Synthesis (ISSS '01), September-October 2001, Montreal, Quebec, Canada 75-80.

  12. 12.

    http://www.xilinx.com

  13. 13.

    http://www.celoxica.com

  14. 14.

    Edwards M, Fozard B: Rapid prototyping of mixed hardware and software systems. Proceedings of Euromicro Symposium on Digital System Design, September 2002, Dortmund, Germany 118-125.

  15. 15.

    Mc Curry P, Morgan F, Kilmartin L: Xilinx FPGA implementation of an image classifier for object detection applications. Proceedings of IEEE International Conference on Image Processing (ICIP '01), October 2001, Thessaloniki, Greece 3: 346-349.

  16. 16.

    Lauwereins R, Engels M, Ade M, Peperstraete JA: Grape-II: a system-level prototyping environment for DSP applications. Computer 1995,28(2):35-43. 10.1109/2.347998

  17. 17.

    Gajski DD, Ramachandran L: Introduction to high-level synthesis. IEEE Design and Test of Computers 1994,11(4):44-54. 10.1109/54.329454

  18. 18.

    Benkrid K, Belkacemi S: Design and implementation of a 2D convolution core for video applications on FPGAs. Proceedings of the 3rd International Workshop on Digital and Computational Video (DCV '02), November 2002, Clearwater Beach, Fla, USA 85-92.

  19. 19.

    Schmit H, Thomas DE: Synthesis of application-specific memory designs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1997,5(1):101-111. 10.1109/92.555990

  20. 20.

    Jha PK, Dutt ND: High-level library mapping for memories. ACM Transactions on Design Automation of Electronic Systems 2000,5(3):566-603. 10.1145/348019.348297

  21. 21.

    Lawal N, Thörnberg B, O'Nils M, Norell H: Global block RAM allocation algorithm for FPGA implementation of real-time video processing systems. Journal on Circuits, Systems and Computers 2006.,15(5):

  22. 22.

    Thörnberg B, Olsson L, O'Nils M: Optimization of memory allocation for real-time video processing on FPGA. Proceedings of the International Workshop on Rapid System Prototyping, June 2005, Montreal, Quebec, Canada 141-147.

  23. 23.

    Weinhardt M, Luk W: Memory access optimisation for reconfigurable systems. IEE Proceedings: Computers and Digital Techniques 2001,148(3):105-112. 10.1049/ip-cdt:20010514

  24. 24.

    Diniz P, Park J: Automatic synthesis of data storage and control structures for FPGA-based computing engines. Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '00), April 2000, Napa Valley, Calif, USA 91-100.

  25. 25.

    Ahn JH, Dally WJ, Khailany B, Kapasi UJ, Das A: Evaluating the imagine stream architecture. Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA '04), June 2004, Munich, Germany 14-25.

  26. 26.

    O'Nils M, Thörnberg B, Norell H: A comparison between local and global memory allocation for FPGA implementation of real-time video processing systems. Proocedings of the IEEE International Conference on Signals and Electronic System (ICSES '04), September 2004, Poznan, Poland

  27. 27.

    Lawal N, Thörnberg B, O'Nils M: Address generation for FPGA RAMs for efficient implementation of real-time video processing systems. Proceedings of International Conference on Field Programmable Logic and Applications (FPL '05), August 2005, Tampere, Finland 136-141.

  28. 28.

    Lawal N, O'Nils M: Embedded FPGA memory requirements for real-time video processing applications. Proceedings of the 23rd IEEE Norchip Conference, November 2005, Oulu, Finland 206-209.

Download references

Author information

Correspondence to Håkan Norell.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and Permissions

About this article

Keywords

  • Control Structure
  • Control Functionality
  • Require Memory
  • Field Programmable Gate Array
  • Electronic Circuit