Skip to main content


Design Considerations for Scalable High-Performance Vision Systems Embedded in Industrial Print Inspection Machines

Article metrics

  • 1017 Accesses

  • 2 Citations


This paper describes the design of a scalable high-performance vision system which is used in the application area of optical print inspection. The system is able to process hundreds of megabytes of image data per second coming from several high-speed/high-resolution cameras. Due to performance requirements, some functionality has been implemented on dedicated hardware based on a field programmable gate array (FPGA), which is coupled to a high-end digital signal processor (DSP). The paper discusses design considerations like partitioning of image processing algorithms between hardware and software. The main chapters focus on functionality implemented on the FPGA, including low-level image processing algorithms (flat-field correction, image pyramid generation, neighborhood operations) and advanced processing units (programmable arithmetic unit, geometry unit). Verification issues for the complex system are also addressed. The paper concludes with a summary of the FPGA resource usage and some performance results.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18]


  1. 1.

    Fürtler J, Krattenthaler W, Mayer KJ, Penz H, Vrabl A: SIS-Stamp: an integrated inspection system for sheet prints in stamp printing application. Computers in Industry 2005,56(8-9):958-974. 10.1016/j.compind.2005.05.019

  2. 2.

    Davies ER: Machine Vision. Morgan Kaufmann, San Francisco, Calif, USA; 2005.

  3. 3.

    Stein J: Digital Signal Processing: A Computer Science Perspective. John Wiley & Sons, New York, NY, USA; 2000.

  4. 4.

    Salcic Z, Smailagic A: Digital Systems Design and Prototyping Using Field Programmable Logic and Hardware Description Languages. Kluwer Academic, Dordrecht, The Netherlands; 2000.

  5. 5.

    Rössler P, Eckel C, Nachtnebel H, Fürtler J, Cadek G: FPGA-Design für ein Hochleistungs-bildverarbeitungssystem. Proceedings of the Austrochip 2004, The Austrian National Conference on Microelectronics, October 2004, Villach, Austria 83-88.

  6. 6.

    Fürtler J, Brodersen J, Rössler P, et al.: Architecture for hardware driven image inspection based on FPGAs. Real-Time Image Processing, January 2006, San Jose, Calif, USA, Proceedings of SPIE 6063: 105-113.

  7. 7.

    Fürtler J, Mayer KJ, Krattenthaler W, Bajla I: SPOT—development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing. Real-Time Imaging 2003,9(6):387-399. 10.1016/j.rti.2003.09.017

  8. 8.

    Siegel S: A unified streaming memory controller and its utility in image processing applications. In White Paper. Datacube, AIA Machine Vision Online, Ann Arbor, Mich, USA;

  9. 9.

    Turley J: The Essential Guide to Semiconductors. Prentice-Hall, Upper Saddle River, NJ, USA; 2003.

  10. 10.

    "128MB, 256MB, 512MB (x64, SR) PC3200 200-PIN DDR SODIMM," Datasheet, Micron Technology, 2004

  11. 11.

    Brodersen J, Mayer KJ, Landl D, Bajla I: Novel data acquisition and communication bus architecture for real-time multisensor imaging systems. Real-Time Imaging VII, January 2003, Santa Clara, Calif, USA, Proceedings of SPIE 5012: 122-131.

  12. 12.

    Brodersen J, Palkovich R, Landl D, Fürtler J, Dulovits M: Advanced real-time bus system for concurrent data paths used in high-performance image processing. Real-Time Imaging VIII, January 2004, San Jose, Calif, USA, Proceedings of SPIE 5297: 278-286.

  13. 13.

    Strat ix Device Handbook S5V1-3.1 and S5V2-3.1, Altera, San Jose, Calif, USA

  14. 14.

    DDR SDRAM Controller MegaCore Function User Guide Document Version 1.2.0 rev 1, Altera, San Jose, Calif, USA, March 2003

  15. 15.

    Jähne B: Digital Image Processing. Springer, New York, NY, USA; 1991.

  16. 16.

    Fürtler J, Mayer KJ, Eckel C, Brodersen J, Nachtnebel H, Cadek G: Geometry unit for analysis of warped image features on programmable chips. to appear in EURASIP Journal on Embedded Systems, special issue on Embedded Vision Systems

  17. 17.

    Penz H, Bajla I, Mayer KJ, Krattenthaler W: High-speed template matching with point correlation in image pyramids. Diagnostic Imaging Technologies and Industrial Applications, June 1999, Munich, Germany, Proceedings of SPIE 3827: 85-94.

  18. 18.

    Bergeron J: Writing Testbenches, Functional Verification of HDL Models. 2nd edition. Kluwer Academic, Dordrecht, The Netherlands; 2003.

Download references

Author information

Correspondence to Johannes Fürtler.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and Permissions

About this article


  • Field Programmable Gate Array
  • Design Consideration
  • Digital Signal Processor
  • Image Processing Algorithm
  • Dedicated Hardware