Open Access

Estimation of Power Consumption at Behavioral Modeling Level Using SystemC

EURASIP Journal on Embedded Systems20072007:068673

https://doi.org/10.1155/2007/68673

Received: 22 May 2006

Accepted: 6 May 2007

Published: 14 June 2007

Abstract

A successful embedded system design requires thorough domain analysis and design space exploration. The aim is to develop a target system, which implements the prescribed functionality and at the same time meets the design, time, and cost-related constraints. The early evaluation of design characteristics, such as power consumption, allows the user to take advantage of many architectural design options available and to modify the system architecture, if needed. Currently, SystemC is used to model the hardware and software parts of a system at the high level. However, the characteristics of the modeled system are obtained only at the late design stages during physical synthesis. Here, we present a framework for power estimation at the modeling level of a design using macromodels. The SystemC class library is modified and extended with new classes describing the computation of power characteristics of the behavioral-level hardware models.

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Authors’ Affiliations

(1)
Department of Software Engineering, Faculty of Informatics, Kaunas University of Technology

References

  1. Lavagno L, Martin G, Selic BV (Eds): UML for Real: Design of Embedded Real-Time Systems. Springer, New York, NY, USA; 2003.Google Scholar
  2. Martin G, Chang H (Eds): Winning the SoC Revolution: Experiences in Real Design. Springer, New York, NY, USA; 2003.Google Scholar
  3. Grötker T, Liao S, Martin G, Swan S: System Design with SystemC. Springer, New York, NY, USA; 2002.Google Scholar
  4. Talarico C, Rozenblit JW, Malhotra V, Stritter A: A new framework for power estimation of embedded systems. Computer 2005,38(2):71-78. 10.1109/MC.2005.39View ArticleGoogle Scholar
  5. Darringer JA, Bergamaschi RA, Bhattacharya S, et al.: Early analysis tools for system-on-a-chip design. IBM Journal of Research and Development 2002,46(6):691-708. 10.1147/rd.466.0691View ArticleGoogle Scholar
  6. Albanese L: Restoring predictability in SoC integration. EETimes 2004.Google Scholar
  7. Li Y, Henkel J: A framework for estimating and minimizing energy dissipation of embedded HW/SW systems. Proceedings of the 35th Design Automation Conference (DAC '98), June 1998, San Francisco, Calif, USA 188-193.Google Scholar
  8. Lahiri K, Raghunathan A, Dey S: Efficient power profiling for battery-driven embedded system design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2004,23(6):919-932. 10.1109/TCAD.2004.828137View ArticleGoogle Scholar
  9. Rabaey JM, Pedram M (Eds): Low Power Design Methodologies. Kluwer Academic Publishers, Norwell, Mass, USA; 1996.Google Scholar
  10. Raghunathan A, Jha NK, Dey S: High-Level Power Analysis and Optimization. Kluwer Academic Publishers, Norwell, Mass, USA; 1998.MATHView ArticleGoogle Scholar
  11. Macii E, Pedram M, Somenzi F: High-level power modeling, estimation, and optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1998,17(11):1061-1079. 10.1109/43.736181View ArticleGoogle Scholar
  12. Kang SM: Accurate simulation of power dissipation in VLSI circuits. IEEE Journal of Solid-State Circuits 1986,21(5):889-891. 10.1109/JSSC.1986.1052622View ArticleGoogle Scholar
  13. Krodel TH: PowerPlay—fast dynamic power estimation based on logic simulation. Proceedings of IEEE International Conference on Computer Design (ICCD '91), October 1991, Cambridge, Mass, USA 96-100.Google Scholar
  14. Ravi S, Raghunathan A, Chakradhar ST: Efficient RTL power estimation for large designs. Proceedings of the 16th International Conference on VLSI Design, January 2003, New Delhi, India 431-439.Google Scholar
  15. Krishna V, Ranganathan N: A methodology for high level power estimation and exploration. Proceedings of the 8th IEEE Great Lakes Symposium on VLSI, February 1998, Lafayette, La, USA 420-425.Google Scholar
  16. Raghunathan A, Dey S, Jha NK: Register-transfer level estimation techniques for switching activity and power consumption. Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '96), November 1996, San Jose, Calif, USA 158-165.View ArticleGoogle Scholar
  17. Arts B, Eng N, Heijligers MJM, et al.: Statistical power estimation of behavioral descriptions. In Proceedings of the 13th International Workshop on Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation (PATMOS '03), September 2003, Torino, Italy, Lecture Notes in Computer Science. Volume 2799. Springer; 197-207.View ArticleGoogle Scholar
  18. Ferrandi F, Fummi F, Macii E, Poncino M: Power estimation of behavioral descriptions. Proceedings of Design, Automation and Test in Europe (DATE '98), February 1998, Paris, France 762-766.View ArticleGoogle Scholar
  19. Mehra R, Rabaey J: Behavioral level power estimation and exploration. Proceedings of the 1st International Workshop on Low Power Design, April 1994, Napa Valley, Calif, USA 197-202.Google Scholar
  20. Abril A, Mehrez H, Petrot F, Gobert J, Miro C: Energy estimation and optimization in architectural descriptions of complex embedded systems. VLSI Circuits and Systems II, May 2005, Seville, Spain, Proceedings of SPIE 5837: 456-466.View ArticleGoogle Scholar
  21. Brooks D, Tiwari V, Martonosi M: Wattch: a framework for architectural-level power analysis and optimizations. Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA '00), June 2000, Vancouver, BC, Canada 83-94.Google Scholar
  22. Schirrmeister F: Design for Low-Power at the Electronic System Level. ChipVision Design Systems, White paper, 2004Google Scholar
  23. Xanthos S, Chatzigeorgiou A, Stephanides G: Energy estimation with systemC: a programmer's perspective. In Proceedings of the 7th International Conference on Systems Computational Methods in Circuits and Systems Applications, July 2003, Corfu, Greece. WSEAS Press; 1-6.Google Scholar
  24. Lajolo M, Raghunathan A, Dey S, Lavagno L: Efficient power co-estimation techniques for system-on-chip design. Proceedings of Design, Automation and Test in Europe (DATE '00), March 2000, Paris, France 27-34.View ArticleGoogle Scholar
  25. Bansal N, Lahiri K, Raghunathan A, Chakradhar ST: Power monitors: a framework for system-level power estimation using heterogeneous power models. Proceedings of the 18th IEEE International Conference on VLSI Design, January 2005, Kolkata, India 579-585.Google Scholar
  26. Nemani M, Najm F: Towards a high-level power estimation capability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1996,15(6):588-598. 10.1109/43.503929View ArticleGoogle Scholar
  27. Fornaciari W, Gubian P, Sciuto D, Silvano C: Power estimation of embedded systems: a hardware/software codesign approach. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1998,6(2):266-275. 10.1109/92.678887View ArticleGoogle Scholar
  28. Damaševičius R: Estimation of design characteristics at RTL modeling level using systemC. Information Technology and Control 2006,35(2):117-123.Google Scholar
  29. Bernacchia G, Papaefthymiou MC: Analytical macromodeling for high-level power estimation. Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '99), November 1999, San Jose, Calif, USA 280-283.Google Scholar
  30. Bogliolo A, Benini L: Robust RTL power macromodels. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1998,6(4):578-581. 10.1109/92.736131View ArticleGoogle Scholar
  31. Bogliolo A, Benini L, De Micheli G: Regression-based RTL power modeling. ACM Transactions on Design Automation of Electronic Systems 2000,5(3):337-372. 10.1145/348019.348081View ArticleGoogle Scholar
  32. Gupta S, Najm FN: Analytical models for RTL power estimation of combinational and sequential circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2000,19(7):808-814. 10.1109/43.851996View ArticleGoogle Scholar
  33. Zafalon R, Rossello M, Macii E, Poncino M: Power macromodeling for a high quality RT-level power estimation. Proceedings of the 1st IEEE International Symposium on Quality of Electronic Design (ISQED '00), March 2000, San Jose, Calif, USA 59-63.Google Scholar
  34. Benini L, De Micheli G: Dynamic Power Management: Design Techniques and CAD Tools. Kluwer Academic Publishers, Norwell, Mass, USA; 1997.Google Scholar
  35. Shang L, Jha NK: High-level power modeling of CPLDs and FPGAs. Proceedings of the 19th IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD '01), September 2001, Austin, Tex, USA 46-53.Google Scholar

Copyright

© R. Damaševičius and V. Štuikys. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.