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Hardware Architecture of Reinforcement Learning Scheme for Dynamic Power Management in Embedded Systems

Abstract

Dynamic power management (DPM) is a technique to reduce power consumption of electronic systems by selectively shutting down idle components. In this paper, a novel and nontrivial enhancement of conventional reinforcement learning (RL) is adopted to choose the optimal policy out of the existing DPM policies. A hardware architecture evolved from the VHDL model of Temporal Difference RL algorithm is proposed in this paper, which can suggest the winner policy to be adopted for any given workload to achieve power savings. The effectiveness of this approach is also demonstrated by an event-driven simulator, which is designed using JAVA for power-manageable embedded devices. The results show that RL applied to DPM can lead up to 28% power savings.

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Correspondence to Viswanathan Lakshmi Prabha.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Prabha, V.L., Monie, E.C. Hardware Architecture of Reinforcement Learning Scheme for Dynamic Power Management in Embedded Systems. J Embedded Systems 2007, 065478 (2007). https://doi.org/10.1155/2007/65478

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Keywords

  • Optimal Policy
  • Reinforcement Learning
  • Electronic Circuit
  • Power Saving
  • Hardware Architecture