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  • Research Article
  • Open Access

Hardware Architecture of Reinforcement Learning Scheme for Dynamic Power Management in Embedded Systems

EURASIP Journal on Embedded Systems20072007:065478

  • Received: 6 July 2006
  • Accepted: 28 May 2007
  • Published:


Dynamic power management (DPM) is a technique to reduce power consumption of electronic systems by selectively shutting down idle components. In this paper, a novel and nontrivial enhancement of conventional reinforcement learning (RL) is adopted to choose the optimal policy out of the existing DPM policies. A hardware architecture evolved from the VHDL model of Temporal Difference RL algorithm is proposed in this paper, which can suggest the winner policy to be adopted for any given workload to achieve power savings. The effectiveness of this approach is also demonstrated by an event-driven simulator, which is designed using JAVA for power-manageable embedded devices. The results show that RL applied to DPM can lead up to 28% power savings.


  • Optimal Policy
  • Reinforcement Learning
  • Electronic Circuit
  • Power Saving
  • Hardware Architecture

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Authors’ Affiliations

Department of Electronics and Communication Engineering, Government College of Technology, Coimbatore, Tamil Nadu, 641-013, India
Thanthai Periyar Government Institute of Technology TPGIT, Vellore, Tamil Nadu, 632002, India


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© Prabha and Monie 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.