Skip to main content
EURASIP Journal on Embedded Systems
Download PDF
  • Research Article
  • Open access
  • Published:

Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths

EURASIP Journal on Embedded Systems volume 2007, Article number: 065173 (2006) Cite this article

Abstract

Compilers for reconfigurable computers aim to generate problem-specific optimized datapaths for kernels extracted from an input language. In many cases, however, judicious use of preexisting manually optimized IP blocks within these datapaths could improve the compute performance even further. The integration of IP blocks into the compiled datapaths poses a different set of problems than stitching together IPs to form a system-on-chip; though, instead of the loose coupling using standard busses employed by SoCs, the one between datapath and IP block must be much tighter. To this end, we propose a concise language that can be efficiently synthesized using a template-based approach for automatically generating lightweight data and control interfaces at the datapath level.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24]

References

  1. Li Y, Callahan T, Darnell E, Harr R, Kurkure U, Stockwood J: Hardware-software co-design of embedded reconfigurable architectures. Proceedings of 37th Design Automation Conference (DAC '00), June 2000, Los Angeles, Calif, USA 507-512.

    Chapter  Google Scholar 

  2. Kasprzyk N, Koch A: High-level-language compilation for reconfigurable computers. Proceedings of European Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoc '05), June 2005, Montpellier, France

    Google Scholar 

  3. VSI Alliance : Virtual Component Interface Standard Version 2. 2001.http://www.vsia.org

    Google Scholar 

  4. ARM : AMBA Specification Rev 2.0. 2001.http://www.arm.com/products/solutions/AMBA_Spec.html

    Google Scholar 

  5. IBM : Core Connect Bus Architecture. 1999.http://www-3.ibm.com/chips/techlib/techlib.nsf/productfamilies/CoreConnect_Bus_Architecture

    Google Scholar 

  6. Koch A: On tool integration in high-performance FPGA design flows. Proceedings of 9th International Workshop on Field-Programmable Logic and Applications (FPL '99), August-September 1999, Glasgow, UK 165-174.

    Chapter  Google Scholar 

  7. Koch A: FLAME: a flexible API for module based environments. In Tech. Rep. 2004-01. EIS, Technical University of Braunschweig, Braunschweig, Germany; 2004.

    Google Scholar 

  8. Passerone R, Rowson JA, Sangiovanni-Vincentelli A: Automatic synthesis of interfaces between incompatible protocols. Proceedings of 35th Design Automation Conference (DAC '98), June 1998, San Francisco, Calif, USA 8-13.

    Google Scholar 

  9. Sun JS, Brodersen RW: Design of system interface modules. Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '92), November 1992, Santa Clara, Calif, USA 478-481.

    Google Scholar 

  10. Lin B, Vercauteren S: Synthesis of concurrent system interface modules with automatic protocol conversion generation. Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '94), November 1994, San Jose, Calif, USA 101-108.

    Google Scholar 

  11. Chou P, Ortega RB, Borriello G: Interface co-synthesis techniques for embedded systems. Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '95), November 1995, San Jose, Calif, USA 280-287.

    Chapter  Google Scholar 

  12. D'silva V, Sowmya A, Parameswaran S, Ramesh S: A formal approach to interface synthesis for system-on-chip design. In Tech. Rep. UNSW-CSE-TR-304. University of New South Wales, Sydney, Australia; 2003.

    Google Scholar 

  13. Smith J, De Micheli G: Automated composition of hardware components. Proceedings of 35th Design Automation Conference (DAC '98), June 1998, San Francisco, Calif, USA 14-19.

    Google Scholar 

  14. Narayan S, Gajski DD: Interfacing incompatible protocols using interface process generation. Proceedings of 32nd Design Automation Conference (DAC '95), June 1995, San Francisco, Calif, USA 468-473.

    Google Scholar 

  15. Jung H, Lee K, Ha S: Efficient hardware controller synthesis for synchronous dataflow graph in system level design. Proceedings of 13th International Symposium on System Synthesis (ISSS '00), September 2000, Madrid, Spain 79-84.

    Chapter  Google Scholar 

  16. Teifel J, Manohar R: Static tokens: using dataflow to automate concurrent pipeline synthesis. Proceedings of 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '04), April 2004, Crete, Greece 17-27.

    Google Scholar 

  17. Lange H, Koch A: Memory access schemes for configurable processors. Proceedings of 10th International Workshop on Field-Programmable Logic and Applications (FPL '00), August 2000, Villach, Austria 615-625.

    Google Scholar 

  18. Sentovich EM, Singh KJ, Lavagno L, et al.: SIS: a system for sequential circuit synthesis. In Tech. Rep. UCB/ERL M92/41. Electrical Engineering and Computer Sciences Department, University of California, Berkeley, Calif, USA; 1992.

    Google Scholar 

  19. Cong J, Ding Y: FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1994,13(1):1-12. 10.1109/43.273754

    Article  Google Scholar 

  20. Neumann T, Koch A: A generic library for adaptive computing environments. Proceedings of 11th International Conference on Field-Programmable Logic and Applications (FPL '01), August 2001, Belfast, Northern Ireland, UK 503-512.

    Chapter  Google Scholar 

  21. Lange H, Koch A: Hardware/software-codesign by automatic embedding of complex IP cores. Proceedings of 14th International Conference on Field Programmable Logic and Application (FPL '04), August-September 2004, Leuven, Belgium 679-689.

    Google Scholar 

  22. Xilinx : High-Performance 16-Point Complex FFT/IFFT V1.0. product specification, 2001

  23. Davidson ES, Shar LE, Thomas AT, Patel JH: Effective control for pipelined computers. Proceedings of 10th IEEE Computer Society International Conference (COMPCON '75), February 1975, San Francisco, Calif, USA 181-184.

    Google Scholar 

  24. Schaumont P, Vanthournout B, Bolsens I, De Man H: Synthesis of pipelined DSP accelerators with dynamic scheduling. Proceedings of 8th International Symposium on System Synthesis (ISSS '95), September 1995, Cannes, France 72-77.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Embedded Systems and Applications Group, Technical University of Darmstadt, FB20, Hochschulstraße 11, Darmstadt, 64289, Germany

    Andreas Koch

Authors
  1. Andreas Koch
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Andreas Koch.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and permissions

About this article

Cite this article

Koch, A. Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths. J Embedded Systems 2007, 065173 (2006). https://doi.org/10.1155/2007/65173

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1155/2007/65173

Keywords