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EURASIP Journal on Embedded Systems
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A Systematic Approach to Design Low-Power Video Codec Cores

EURASIP Journal on Embedded Systems volume 2007, Article number: 064569 (2007) Cite this article

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Abstract

The higher resolutions and new functionality of video applications increase their throughput and processing requirements. In contrast, the energy and heat limitations of mobile devices demand low-power video cores. We propose a memory and communication centric design methodology to reach an energy-efficient dedicated implementation. First, memory optimizations are combined with algorithmic tuning. Then, a partitioning exploration introduces parallelism using a cyclo-static dataflow model that also expresses implementation-specific aspects of communication channels. Towards hardware, these channels are implemented as a restricted set of communication primitives. They enable an automated RTL development strategy for rigorous functional verification. The FPGA/ASIC design of an MPEG-4 Simple Profile video codec demonstrates the methodology. The video pipeline exploits the inherent functional parallelism of the codec and contains a tailored memory hierarchy with burst accesses to external memory. 4CIF encoding at 30 fps, consumes 71 mW in a 180 nm, 1.62 V UMC technology.

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Author information

Affiliations

  1. D6, IMEC, Kapeldreef 75, Leuven, 3001, Belgium
    • Kristof Denolf
    •  & Diederik Verkest
  2. Department of Electrical Engineering, Katholieke Universiteit Leuven (KUL), Leuven, 3001, Belgium
    • Diederik Verkest
  3. Department of Electrical Engineering, Vrije Universiteit Brussel (VUB), Brussel, 1050, Belgium
    • Diederik Verkest
  4. Xilinx Inc, 2100 Logic Drive, San Jose, CA, 95124-3400, USA
    • Adrian Chirila-Rus
    • , Paul Schumacher
    • , Robert Turney
    •  & Kees Vissers
  5. Faculty of Electrical Engineering, Technical University Eindhoven, Den Dolech 2, Eindhoven, 5612, AZ, The Netherlands
    • Henk Corporaal
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Corresponding author

Correspondence to Kristof Denolf.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Denolf, K., Chirila-Rus, A., Schumacher, P. et al. A Systematic Approach to Design Low-Power Video Codec Cores. J Embedded Systems 2007, 064569 (2007). https://doi.org/10.1155/2007/64569

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Keywords

  • External Memory
  • Memory Hierarchy
  • Video Codec
  • Algorithmic Tuning
  • Memory Optimization