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The Sandbridge SB3011 Platform
EURASIP Journal on Embedded Systems volume 2007, Article number: 056467 (2007)
Abstract
This paper describes the Sandbridge Sandblaster real-time software-defined radio platform. Specifically, we describe the SB3011 system-on-a-chip multiprocessor. We describe the software development system that enables real-time execution of communications and multimedia applications. We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding. Each processor core achieves 600 MHz at 0.9 V operation while typically dissipating 75 mW in 90 nm technology. The entire chip typically dissipates less than 500 mW at 0.9 V.
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References
Blaauw G, Brooks F Jr.: Computer Architecture: Concepts and Evolution. Addison-Wesley, Reading, Mass, USA; 1997.
Case B: Philips hopes to displace DSPs with VLIW. Microprocessor Report 1997,8(16):12-15.
Kneip J, Weiss M, Drescher W, et al.: Single chip programmable baseband ASSP for 5 GHz wireless LAN applications. IEICE Transactions on Electronics 2002,E85-C(2):359-367.
van Berkel K, Heinle F, Meuwissen PPE, Moerman K, Weiss M: Vector processing as an enabler for software-defined radio in handheld devices. EURASIP Journal on Applied Signal Processing 2005,2005(16):2613-2625. 10.1155/ASP.2005.2613
Robelly JP, Cichon G, Seidel H, Fettweis G: A HW/SW design methodology for embedded SIMD vector signal processors. International Journal of Embedded Systems 2005,1(11):2-10.
Glossner J, Raja T, Hokenek E, Moudgill M: A multithreaded processor architecture for SDR. The Proceedings of the Korean Institute of Communication Sciences 2002,19(11):70-84.
Glossner J, Schulte M, Moudgill M, et al.: Sandblaster low-power multithreaded SDR baseband processor. Proceedings of the 3rd Workshop on Applications Specific Processors (WASP '04), September 2004, Stockholm, Sweden 53-58.
Lee EA: The problem with threads. Computer 2006,39(5):33-42. 10.1109/MC.2006.180
Glossner J, Chirca K, Schulte M, et al.: Sandblaster low power DSP. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '04), October 2004, Orlando, Fla, USA 575-581.
Moyer B: Low-power design for embedded processors. Proceedings of the IEEE 2001,89(11):1576-1587. 10.1109/5.964439
Mudge T: Power: a first-class architectural design constraint. Computer 2001,34(4):52-58. 10.1109/2.917539
Wroblewski A, Schumacher O, Schimpfle CV, Nossek JA: Minimizing gate capacitances with transistor sizing. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '01), May 2001, Sydney, NSW, Australia 4: 186-189.
Borah M, Owens RM, Irwin MJ: Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint. Proceedings of the International Symposium on Low Power Electronics and Design, April 1995, Dana Point, Calif, USA 167-172.
Kim S, Kim J, Hwang S-Y: New path balancing algorithm for glitch power reduction. IEE Proceedings: Circuits, Devices and Systems 2001,148(3):151-156. 10.1049/ip-cds:20010343
Goering R: Platform-based design: a choice, not a panacea. EE Times 2002. http://www.eetimes.com/story/OEG20020911S0061
Silvén O, Jyrkkä K: Observations on power-efficiency trends in mobile communication devices. Proceedings of the 5th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS '05), July 2005, Samos, Greece, Lecture Notes in Computer Science 3553: 142-151.
Schulte M, Glossner J, Mamidi S, Moudgill M, Vassiliadis S: A low-power multithreaded processor for baseband communication systems. In Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, Lecture Notes in Computer Science. Volume 3133. Springer, New York, NY, USA; 2004:393-402.
Nichols B, Buttlar D, Farrell J: Pthreads Programming: A POSIX Standard for Better Multiprocessing, O'Reilly Nutshell Series. O'Reilly Media, Sebastopol, Calif, USA; 1996.
Jarvinen K, Vainio J, Kapanen P, et al.: GSM enhanced full rate speech codec. Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP '97), April 1997, Munich, Germany 2: 771-774.
Kotlyar V, Moudgill M: Detecting overflow detection. Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS '04), September 2004, Stockholm, Sweden 36-41.
Balzola PI, Schulte M, Ruan J, Glossner J, Hokenek E: Design alternatives for parallel saturating multioperand adders. Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD '01), September 2001, Austin, Tex, USA 172-177.
Lin Y, Lee H, Woh M, et al.: SODA: a low-power architecture for software radio. Proceedings of the 33rd International Symposium on Computer Architecture (ISCA '06), June 2006, Boston, Mass, USA 89-100.
Lodi A, Cappelli A, Bocchi M, et al.: XiSystem: a XiRisc-based SoC with reconfigurable IO module. IEEE Journal of Solid-State Circuits 2006,41(1):85-96. 10.1109/JSSC.2005.859319
Duller A, Panesar G, Towner D: Parallel processing - the picoChip way! Communicating Process Architectures (CPA '03), September 2003, Enschede, The Netherlands 125-138.
Mohebbi B, Filho EC, Maestre R, Davies M, Kurdahi FJ: A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core. Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, October 2003, Newport Beach, Calif, USA 103-108.
Ungerer T, Robič B, Šilc J: A survey of processors with explicit multithreading. ACM Computing Surveys 2003,35(1):29-63. 10.1145/641865.641867
Smith BJ: The architecture of HEP. In Parallel MIMD Computation: HEP Supercomputer and Its Applications. Edited by: Kowalik JS. MIT Press, Cambridge, Mass, USA; 1985:41-55.
Mankovic TE, Popescu V, Sullivan H: CHoPP principles of operations. Proceedings of the 2nd International Supercomputer Conference, May 1987, Mannheim, Germany 2-10.
Tullsen DM, Eggers SJ, Levy HM: Simultaneous multithreading: maximizing on-chip parallelism. Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA '95), June 1995, Santa Margherita Ligure, Italy 392-403.
Parson D, Beatty P, Glossner J, Schlieder B: A framework for simulating heterogeneous virtual processors. Proceedings of the 32nd Annual Simulation Symposium, April 1999, San Diego, Calif, USA 58-67.
Leupers R, Elste J, Landwehr B: Generation of interpretive and compiled instruction set simulators. Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '99), January 1999, Wanchai, Hong Kong 1: 339-342.
Zivojnovic V, Tjiang S, Meyr H: Compiled simulation of programmable DSP architectures. Proceedings of the IEEE Workshop on VLSI Signal Processing, October 1995, Osaka, Japan 187-196.
Pees S, Hoffmann A, Zivojnovic V, Meyr H: LISA—machine description language for cycle-accurate models of programmable DSP architectures. Proceedings of the 36th Annual Design Automation Conference (DAC '99), June 1999, New Orleans, La, USA 933-938.
Zhu J, Gajski DD: An ultra-fast instruction set simulator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2002,10(3):363-373.
Cmelik R, Keppel D: Shade: a fast instruction-set simulator for execution profiling. In Tech. Rep. UWCSE 93-06-06. University of Washington, Washington, DC, USA; 1993.
Nohl A, Braun G, Schliebusch O, Leupers R, Meyr H, Hoffmann A: Design innovations for embedded processors: a universal technique for fast and flexible instruction-set architecture simulation. In Proceedings of the 39th Design Automation Conference (DAC '02), June 2002, New Orleans, La, USA. ACM Press; 22-27.
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Glossner, J., Iancu, D., Moudgill, M. et al. The Sandbridge SB3011 Platform. J Embedded Systems 2007, 056467 (2007). https://doi.org/10.1155/2007/56467
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DOI: https://doi.org/10.1155/2007/56467