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EURASIP Journal on Embedded Systems

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  • Research Article
  • Open Access

Application-Specific Instruction Set Processor Implementation of List Sphere Detector

  • 1Email author,
  • 2,
  • 1,
  • 1,
  • 2 and
  • 1
EURASIP Journal on Embedded Systems20082007:054173

https://doi.org/10.1155/2007/54173

©  Juho Antikainen et al. 2007

Received: 8 June 2007

Accepted: 12 November 2007

Published: 8 January 2008

Abstract

Multiple-input multiple-output (MIMO) technology enables higher transmission capacity without additional frequency spectrum and is becoming a part of many wireless system standards. Sphere detection has been introduced in MIMO systems to achieve maximum likelihood (ML) or near-ML estimation with reduced complexity. This paper reviews related work on sphere detector implementations and presents an application-specific instruction set processor (ASIP) implementation of K-best list sphere detector (LSD) using transport triggered architecture (TTA). The implementation is based on using memory and heap data structure for symbol vector sorting. The design space is explored by presenting several variations of the implementation and comparing them with each other in terms of their latencies and hardware complexities. An early proposal for a parallelized architecture with a decoding throughput of approximately 5.3 Mbps is presented

Keywords

  • MIMO System
  • Transmission Capacity
  • Hardware Complexity
  • Symbol Vector
  • ASIP

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Authors’ Affiliations

(1)
Information Processing Laboratory and Centre for Wireless Communications, University of Oulu, Oulu, Finland
(2)
Institute of Digital and Computer Systems, Tampere University of Technology, Tampere, Finland

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Copyright

© Juho Antikainen et al. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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