Skip to content


  • Research Article
  • Open Access

PfeLib—A Performance Primitives Library for Embedded Vision

EURASIP Journal on Embedded Systems20062007:049051

  • Received: 30 April 2006
  • Accepted: 14 September 2006
  • Published:


This paper presents our work on PfeLib—a high performance software library for image processing and computer vision algorithms for an embedded system. The main target platform for PfeLib is the TMS320C6000 series of digital signal processors (DSPs) from Texas instruments. PfeLib contains several new approaches for problems that are typical when developing software for embedded systems. We propose a method for image data transfer from a development host (PC) to an embedded system for test and verification. This enables step-by-step performance optimizations directly on the target platform. An optimization procedure is described that illustrates our approach for obtaining the best possible DSP performance with a reasonable development effort. Speedup improvement factors of up to 16 were achieved. Also, the problem of the limited on-chip memory on DSPs is addressed by a novel double buffering method using direct memory access (DMA), called resource optimized slicing (ROS-DMA). ROS-DMA is intended to be used instead of L2 cache and it is a core component of PfeLib—it achieves up to six times faster image processing as compared to using L2 cache.


  • Embed System
  • Digital Signal Processor
  • Software Library
  • Texas Instrument
  • Direct Memory Access

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21]

Authors’ Affiliations

Austrian Research Centers GmbH-ARC, Donau-City-Street 1, Vienna, 1220, Austria


  1. Zinner C, Kubinger W: ROS-DMA: a DMA double buffering method for embedded image processing with resource optimized slicing. Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS '06), April 2006, San Jose, Calif, USA 361-372.View ArticleGoogle Scholar
  2. Borbély S, Kogler J, Kubinger W: In-the-loop simulation of embedded computer vision applications. Proceedings of the 9th International IASTED Conference on Software Engineering and Applications (SEA '05), November 2005, Phoenix, Ariz, USA Google Scholar
  3. Behringer R, Travis W, Daily R, et al.: RASCAL - an autonous ground vehicle for desert driving in the DARPA grand challenge 2005. Proceedings of the 8th International IEEE Conference on Intelligent Transportation Systems (ITSC '05), September 2005, St. Louis, Mo, USA Google Scholar
  4. Kogler J, Hemetsberger H, Alefs B, Kubinger W, Travis W: Embedded stereo vision system for intelligent autonomous vehicles. Proceedings of the IEEE Intelligent Vehicle Symposium (IV '06), June 2006, Tokyo, Japan 64-69.Google Scholar
  5. Texas Instruments Incorporated. TMS320C6000 Technical Brief, February 1999. Literature Number: SPRU197DGoogle Scholar
  6. Intel Corporation : Intel Integrated Performance Primitives for Intel Architecture. 2004. Document Number:A70805-014, Version-014Google Scholar
  7. Kisaicanin B: Examples of low-level computer vision on media processors. Proceedings of IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR '05), June 2005, San Diego, Calif, USA 3: 135.Google Scholar
  8. Qureshi S: Embedded Image Processing on the TMS320C6000TM DSP. 1st edition. Springer, New York, NY, USA; 2005.Google Scholar
  9. Chassaing R: Digital Signal Processing and Applications with the C6713 and C6416 DSK. John Wiley & Sons, New York, NY, USA; 2005.Google Scholar
  10. Lam M: Software pipelining: an effective scheduling technique for VLIW machines. Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '88), June 1988, Atlanta, Ga, USA 318-328.Google Scholar
  11. Allan VH, Jones RB, Lee RM, Allan SJ: Software pipelining. ACM Computing Surveys 1995,27(3):367-432. 10.1145/212094.212131View ArticleGoogle Scholar
  12. Fürtler J, Mayer KJ, Krattenthaler W, Bajla I: SPOT-Development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing. Real-Time Imaging 2003,9(6):387-399. 10.1016/j.rti.2003.09.017View ArticleGoogle Scholar
  13. Texas Instruments Incorporated. TMS320C6000 Optimizing Compiler User's Guide, May 2004. Literature Number: SPRU187LGoogle Scholar
  14. Texas Instruments Incorporated. TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide, June 2005. Literature Number: SPRU732AGoogle Scholar
  15. Spectrum Digital, Incorporated 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 USA, June 2005Google Scholar
  16. Texas Instruments Incorporated. DSP/BIOS, RTDX and Host-Target Communications, February 2003. Literature Number: SPRA895Google Scholar
  17. Pizzolato D: CxImage. April 2005,
  18. Texas Instruments Incorporated. XDS560 Emulator Technical Reference, April 2002. Literature Number: SPRU589Google Scholar
  19. Brainard DH: Bayesian method for reconstructing color images from trichromatic samples. Proceedings of the IS&T 47th Annual Meeting, May 1994, Rochester, NY, USA 375-380.Google Scholar
  20. Furtner U: Color processing with Bayer Mosaic sensors. August 2001,
  21. Sonka M, Hlavac V, Roger B: Image Processing Analysis and Machine Vision. 2nd edition. PWS, Boston, Mass, USA; 1999.Google Scholar


© Christian Zinner et al. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.