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Thermal-Aware Scheduling for Future Chip Multiprocessors

EURASIP Journal on Embedded Systems volume 2007, Article number: 048926 (2007) Cite this article

Abstract

The increased complexity and operating frequency in current single chip microprocessors is resulting in a decrease in the performance improvements. Consequently, major manufacturers offer chip multiprocessor (CMP) architectures in order to keep up with the expected performance gains. This architecture is successfully being introduced in many markets including that of the embedded systems. Nevertheless, the integration of several cores onto the same chip may lead to increased heat dissipation and consequently additional costs for cooling, higher power consumption, decrease of the reliability, and thermal-induced performance loss, among others. In this paper, we analyze the evolution of the thermal issues for the future chip multiprocessor architectures and show that as the number of on-chip cores increases, the thermal-induced problems will worsen. In addition, we present several scenarios that result in excessive thermal stress to the CMP chip or significant performance loss. In order to minimize or even eliminate these problems, we propose thermal-aware scheduler (TAS) algorithms. When assigning processes to cores, TAS takes their temperature and cooling ability into account in order to avoid thermal stress and at the same time improve the performance. Experimental results have shown that a TAS algorithm that considers also the temperatures of neighboring cores is able to significantly reduce the temperature-induced performance loss while at the same time, decrease the chip's temperature across many different operation and configuration scenarios.

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Authors and Affiliations

  1. Department of Computer Science, University of Cyprus, 75 Kallipoleos Street, P.O. Box 20537, Nicosia, 1678, Cyprus

    Kyriakos Stavrou & Pedro Trancoso

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  1. Kyriakos Stavrou
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  2. Pedro Trancoso
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Correspondence to Kyriakos Stavrou.

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Stavrou, K., Trancoso, P. Thermal-Aware Scheduling for Future Chip Multiprocessors. J Embedded Systems 2007, 048926 (2007). https://doi.org/10.1155/2007/48926

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