Open Access

Thermal-Aware Scheduling for Future Chip Multiprocessors

EURASIP Journal on Embedded Systems20072007:048926

https://doi.org/10.1155/2007/48926

Received: 10 July 2006

Accepted: 29 January 2007

Published: 11 April 2007

Abstract

The increased complexity and operating frequency in current single chip microprocessors is resulting in a decrease in the performance improvements. Consequently, major manufacturers offer chip multiprocessor (CMP) architectures in order to keep up with the expected performance gains. This architecture is successfully being introduced in many markets including that of the embedded systems. Nevertheless, the integration of several cores onto the same chip may lead to increased heat dissipation and consequently additional costs for cooling, higher power consumption, decrease of the reliability, and thermal-induced performance loss, among others. In this paper, we analyze the evolution of the thermal issues for the future chip multiprocessor architectures and show that as the number of on-chip cores increases, the thermal-induced problems will worsen. In addition, we present several scenarios that result in excessive thermal stress to the CMP chip or significant performance loss. In order to minimize or even eliminate these problems, we propose thermal-aware scheduler (TAS) algorithms. When assigning processes to cores, TAS takes their temperature and cooling ability into account in order to avoid thermal stress and at the same time improve the performance. Experimental results have shown that a TAS algorithm that considers also the temperatures of neighboring cores is able to significantly reduce the temperature-induced performance loss while at the same time, decrease the chip's temperature across many different operation and configuration scenarios.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41]

Authors’ Affiliations

(1)
Department of Computer Science, University of Cyprus

References

  1. Agarwal V, Hrishikesh MS, Keckler SW, Burger D: Clock rate versus IPC: the end of the road for conventional microarchitectures. In Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA '00), June 2000, Vancouver, BC, Canada. ACM Press; 248-259.Google Scholar
  2. Olukotun K, Nayfeh BA, Hammond L, Wilson K, Chang K: The case for a single-chip multiprocessor. In Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '96), October 1996, Cambridge, Mass, USA. ACM Press; 2-11.Google Scholar
  3. Mudge T: Power: a first-class architectural design constraint. Computer 2001,34(4):52-58. 10.1109/2.917539View ArticleGoogle Scholar
  4. Skadron K, Stan MR, Huang W, Velusamy S, Sankaranarayanan K, Tarjan D: Temperature-aware microarchitecture: extended discussion and results. In Tech. Rep. TR-CS-2003-08. University of Virginia, Charlottesville, Va, USA; 2003.Google Scholar
  5. Viswanath R, Wakharkar V, Watwe A, Lebonheur V: Thermal performance challenges from silicon to systems. Intel Technology Journal 2000,4(3):16.Google Scholar
  6. Gunther SH, Binns F, Carmean DM, Hall JC: Managing the impact of increasing microprocessor power consumption. Intel Technology Journal 2001,5(1):9.Google Scholar
  7. Liao W, He L: Coupled power and thermal simulation with active cooling. Proceedings of the 3rd International Workshop on Power-Aware Computer Systems (PACS '03), December 2003, San Diego, Calif, USA, Lecture Notes in Computer Science 3164: 148-163.View ArticleGoogle Scholar
  8. Dhodapkar A, Lim CH, Cai G, Daasch WR: TEM 2 P 2 EST : a thermal enabled multi-model power/performance ESTimator. Proceedings of the 1st International Workshop on Power-Aware Computer Systems-Revised Papers (PACS '00), November 2000, Cambridge, Mass, USA 112-125.Google Scholar
  9. Mahajan R, Brown K, Atluri V: The evolution of microprocessor packaging. Intel Technology Journal 2001, 10.Google Scholar
  10. Li Y, Brooks D, Hu Z, Skadron K: Performance, energy, and thermal considerations for SMT and CMP architectures. Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA '05), February 2005, San Francisco, Calif, USA 71-82.Google Scholar
  11. Genossar D, Shamir N: Intel pentium M processor: power estimation, budgeting, optimization and validation. Intel Technology Journal 2003,7(2):44-49.Google Scholar
  12. Mooref J, Chasef J, Ranganathanf P, Sharmaf R: Making scheduling "cool": temperature-aware workload placement in data centers. Proceedings of the USENIX Annual Technical Conference, April 2005, Anaheim, Calif, USA 61-75.Google Scholar
  13. Heo S, Barr K, Asanović K: Reducing power density through activity migration. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '03), August 2003, Seoul, South Korea 217-222.Google Scholar
  14. Lu Z, Huang W, Ghosh S, Lach J, Stan M, Skadron K: Analysis of temporal and spatial temperature gradients for IC reliability. In Tech. Rep. CS-2004-08. University of Virginia, Charlottesville, Va, USA; 2004.Google Scholar
  15. Lu Z, Lach J, Stan M, Skadron K: Banking chip lifetime: opportunities and implementation. Proceedings of the 1st Workshop on High Performance Computing Reliability Issues (HPCRI '05), February 2005, San Francisco, Calif, USA Google Scholar
  16. Bailey C: Modelling the effect of temperature on product reliability. Proceedings of 19th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM '03), March 2003, San Jose, Calif, USA 324-331.Google Scholar
  17. Mukherjee R, Memik SO, Memik G: Temperature-aware resource allocation and binding in high-level synthesis. In Proceedings of the 42nd Design Automation Conference (DAC '05), June 2005, Anaheim, Calif, USA. ACM Press; 196-201.Google Scholar
  18. Kalla R, Sinharoy B, Tendler JM: IBM Power5 chip: a dual-core multithreaded processor. IEEE Micro 2004,24(2):40-47. 10.1109/MM.2004.1289290View ArticleGoogle Scholar
  19. Kongetira P, Aingaran K, Olukotun K: Niagara: a 32-way multithreaded Sparc processor. IEEE Micro 2005,25(2):21-29. 10.1109/MM.2005.35View ArticleGoogle Scholar
  20. Intel : Intel Pentium D Processor Product Information. 2006.http://www.intel.com/products/processor/pentium_d/ Google Scholar
  21. AMD : AMD Athlon 64X2 Dual-Core Processor. 2006.http://www.amd.com/ Google Scholar
  22. Sasanka R, Adve SV, Chen Y-K, Debes E: The energy efficiency of CMP vs. SMT for multimedia workloads. Proceedings of the 18th Annual International Conference on Supercomputing (ICS '04), June-July 2004, Saint-Malo, France 196-206.View ArticleGoogle Scholar
  23. Debes E: Recent changes and future trends in general purpose processor architectures to support image and video applications. Proceedings of IEEE International Conference on Image Processing (ICIP '03), September 2003, Barcelona, Spain 3: 85-88.Google Scholar
  24. Mombers F, Mlynek D: Multithreaded multimedia processor merging on-chip multiprocessors and distributed vector pipelines. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '99), May-June 1999, Orlando, Fla, USA 4: 287-290.Google Scholar
  25. Goodacre J: Understanding the Options for Embedded Multiprocessing. 2003.http://www.techonline.com/community/tech_group/soc/tech_paper/29359 TechOnLine:Google Scholar
  26. Intel : Intel Pentium D Processor Product Information. 2006.http://www.intel.com/products/processor/pentium_d/ Google Scholar
  27. Stavrou K, Trancoso P: Thermal-aware scheduling: a solution for future chip multiprocessors thermal problems. Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD '06), August-September 2006, Dubrovnik, Croatia 123-126.View ArticleGoogle Scholar
  28. Grochowski E, Ronen R, Shen J, Wang H: Best of both latency and throughput. Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD '04), October 2004, San Jose, Calif, USA 236-243.Google Scholar
  29. Stavrou K, Trancoso P: TSIC: thermal scheduling simulator for chip multiprocessors. Proceedings of the 10th Panhellenic Conference on Informatics (PCI '05), November 2005, Volos, Greece, Lecture Notes in Computer Science 3746: 589-599.Google Scholar
  30. Pénzes PI, Nyström M, Martin AJ: Transistor sizing of energy-delay-efficient circuits. Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU '02), December 2002, Monterey, Calif, USA 126-133.View ArticleGoogle Scholar
  31. Ebergen J, Gainsley J, Cunningham P: Transistor sizing: how to control the speed and energy consumption of a circuit. Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '04), April 2004, Crete, Greece 10: 51-61.Google Scholar
  32. Balasubramonian R, Albonesi D, Buyuktosunoglu A, Dwarkadas S: Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. In Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO '00), December 2000, Monterey, Calif, USA. ACM Press; 245-257.View ArticleGoogle Scholar
  33. Manne S, Klauser A, Grunwald D: Pipeline gating: speculation control for energy reduction. Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA '98), June-July 1998, Barcelona, Spain 132-141.Google Scholar
  34. Han Y, Koren I, Moritz CA: Temperature aware floorplanning. Proceedings of the 2nd Workshop on Temperature-Aware Computer Systems (TACS '05), June 2005, Madison, Wis, USA Google Scholar
  35. McGowen R, Poirier CA, Bostak C, et al.: Power and temperature control on a 90-nm Itanium family processor. IEEE Journal of Solid-State Circuits 2006,41(1):229-237. 10.1109/JSSC.2005.859902View ArticleGoogle Scholar
  36. Donald J, Martonosi M: Techniques for multicore thermal management: classification and new exploration. Proceedings of the 33rd International Symposium on Computer Architecture (ISCA '06), June 2006, Boston, Mass, USA 78-88.View ArticleGoogle Scholar
  37. NIST/SEMATECH : Assessing Product Reliability, Chapter 8, e-Handbook of Statistical Methods. http://www.itl.nist.gov/div898/handbook/
  38. Srinivasan J, Adve SV, Bose P, Rivers J, Hu C-K: RAMP: a model for reliability aware microprocessor design. In IBM Research Report RC23048. IBM, White Plains, NY, USA; 2003:26.Google Scholar
  39. Hung W-L, Xie Y, Vijaykrishnan N, Kandemir M, Irwin MJ: Thermal-aware task allocation and scheduling for embedded systems. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE '05), March 2005, Munich, Germany. Volume 2. IEEE Computer Society; 898-899.Google Scholar
  40. Rosinger P, Al-Hashimi B, Chakrabarty K: Rapid generation of thermal-safe test schedules. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE '05), March 2005, Munich, Germany. Volume 2. IEEE Computer Society; 840-845.Google Scholar
  41. ACPI : Advanced Configuration and Power Interface. 2006.http://www.acpi.info/ Google Scholar

Copyright

© K. Stavrou and P. Trancoso. 2007

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.