Skip to main content
EURASIP Journal on Embedded Systems
Download PDF

Prerouted FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System

EURASIP Journal on Embedded Systems volume 2007, Article number: 041867 (2007) Cite this article

Abstract

A method of constructing prerouted FPGA cores, which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing systems, is presented. Two major challenges are considered: how to manage the wires crossing a core's borders; and how to maintain an acceptable level of flexibility for system construction with only a minimum of overhead. In order to maintain FPGA computing performance, it is crucial to thoroughly analyze the issues at the lowest level of device detail in order to ensure that computing circuit encapsulation is as efficient as possible. We present the first methodology that allows a core to scale its interface bandwidth to the maximum available in a routing channel. Cores can be constructed independently from the rest of the system using a framework that is independent of the method used to place and route primitive components within the core. We use an abstract FPGA model and CAD tools that mirror those used in industry. An academic design flow has been modified to include a wire policy and an interface constraints framework that tightly constrains the use of the wires that cross a core's boundaries. Using this tool set we investigate the effect of prerouting on overall system optimality. Abutting cores are instantly connected by colocation of interface wires. Eliminating run-time routing drastically reduces the time taken to construct a system using a set of cores.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30]

References

  1. Wirthlin MJ: Improving functional density through run-time circuit reconfiguration, Ph.D. thesis. Brigham Young University, Provo, Utah, USA; 1997.

    Google Scholar 

  2. Guccione SA, Levi D, Sundararajan P: JBits: a Java based Interface for Reconfigurable Computing. Proceedings of 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD '99), September 1999, Laurel, Md, USA

    Google Scholar 

  3. Blodget B: Pre-route assistant: a routing tool for run-time reconfiguration. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL '00), August 2000, Villach, Austria 797-800.

    Google Scholar 

  4. Keller E: Jroute: a run-time routing API for FPGA hardware. Reconfigurable Architectures Workshop, May 2000, Cancun, Mexico, Lecture Notes in Computer Science 1800: 874-881.

    Google Scholar 

  5. Brebner G: The swappable logic unit: a paradigm for virtual hardware. Proceedings of the 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, April 1997, Napa Valley, Calif, USA 77-86.

    Google Scholar 

  6. Horta EL, Lockwood JW: Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL '04), August-September 2004, Antwerp, Belgium, Lecture Notes in Computer Science 3203: 975-979.

    Google Scholar 

  7. Bazargan K, Kastner R, Sarrafzadeh M: Fast template placement for reconfigurable computing systems. IEEE Design & Test of Computers 2000,17(1):68-83. 10.1109/54.825678

    Article  Google Scholar 

  8. Walder H, Steiger C, Platzner M: Fast online task placement on FPGAs: free space partitioning and 2D-hashing. Proceedings of International Parallel and Distributed Processing Symposium (IPDPS '03), April 2003, Nice, France 178.

    Google Scholar 

  9. Ma J, Athanas P: A JBits-based incremental design environment with non-preemptive refinement for multi-million gate FPGAs. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '03), June 2003, Las Vegas, Nev, USA 118-124.

    Google Scholar 

  10. Ahmadinia A, Bobda C, Fekete S, Teich J, van der Veen J: Optimal routing-conscious dynamic placement for reconfigurable devices. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL '04), August-September 2004, Antwerp, Belgium, Lecture Notes in Computer Science 3203: 847-851.

    Google Scholar 

  11. Wigley G: An operating system for reconfigurable computing, Ph.D. thesis. University of South Australia, Adelaide, South Australia, Australia; 2005.

    Google Scholar 

  12. Kalte H, Koester M, Kettelhoit B, Porrmann M, Rückert U: A comparative study on system approaches for partially reconfigurable architectures. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '04), June 2004, Las Vegas, Nev, USA 70-76.

    Google Scholar 

  13. Bobda C, Majer M, Koch D, Ahmadinia A, Teich J: A dynamic NoC approach for communication in reconfigurable devices. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL '04), August-September 2004, Antwerp, Belgium, Lecture Notes in Computer Science 3203: 1032-1036.

    Google Scholar 

  14. Horta EL, Lockwood JW, Taylor DE, Parlour D: Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. Proceedings of 39th Design Automation Conference (DAC '02), June 2002, New Orleans, La, USA 343-348.

    Google Scholar 

  15. Huebner M, Schuck C, Becker J: Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs. Proceedings 20th International Parallel and Distributed Processing Symposium (IPDPS '06), April 2006, Rhodes Island, Greece 8.

    Google Scholar 

  16. Tessier R: Fast place and route approaches for FPGAs, Ph.D. thesis. Massachusetts Institute of Technology, Cambridge, Mass, USA; 1999.

    Google Scholar 

  17. Sedcole P, Blodget B, Anderson J, Lysaght P, Becker T: Modular partial reconfiguration in virtex FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '05), August 2005, Tampere, Finland 211-216.

    Google Scholar 

  18. Application Notes 290. Two Flows for Partial Reconfiguration Xilinx, Version 1.2, September, 2004

  19. Singh A, Marek-Sadowska M: FPGA interconnect planning. Proceedings of IEEE/ACM International Workshop on System Level Interconnect Prediction, April 2002, Del Mar, Calif, USA 23-30.

    Google Scholar 

  20. Brebner G, Levi D: Networking on chip with platform FPGAs. Proceedings of IEEE International Conference on Field-Programmable Technology (FPT '03), December 2003, Tokyo, Japan 13-20.

    Google Scholar 

  21. Köster M, Porrmann M, Kalte H: Task placement for heterogeneous reconfigurable architectures. Proceedings of IEEE International Conference on Field-Programmable Technology (FPT '05), December 2005, Singapore 43-50.

    Google Scholar 

  22. Lewis D, Ahmed E, Baeckler G, et al.: The Stratix II logic and routing architecture. Proceedings of the ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays (FPGA '05), February 2005, Monterey, Calif, USA 14-20.

    Google Scholar 

  23. Virtex-4 Family Overview Xilinx, Version 1.3, 2005

  24. Lemieux G, Lee E, Tom M, Yu A: Directional and single-driver wires in FPGA interconnect. Proceedings of IEEE International Conference on Field-Programmable Technology (FPT '04), December 2004, Brisbane, Australia 41-48.

    Google Scholar 

  25. Betz V, Rose J, Marquardt A: Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic, Boston, Mass, USA; 1999.

    Book  Google Scholar 

  26. Williams S: Icarus Verilog. January 2006, http://www.icarus.com/eda/verilog

  27. Chen G, Cong J: Simultaneous timing driven clustering and placement for FPGAs. Proceedings of International Conference on Field-Programmable Logic and Applications (FPL '04), August-September 2004, Antwerp, Belgium 158-167.

    Google Scholar 

  28. Oliver TF, Schmidt B, Maskell DL: Reconfigurable architectures for bio-sequence database scanning on FPGAs. IEEE Transactions on Circuits and Systems II: Express Briefs 2005,52(12):851-855. 10.1109/TCSII.2005.853340

    Article  Google Scholar 

  29. Oliver TF, Maskell DL: An FPGA model for developing dynamic circuit computing. Proceedings IEEE International Conference on Field-Programmable Technology (FPT '05), December 2005, Singapore 281-282.

    Google Scholar 

  30. Sankar Y, Rose J: Trading quality for compile time: Ultra-fast placement for FPGAs. Proceedings of the ACM/SIGDA 7th International Symposium on Field-Programmable Gate Arrays (FPGA '99), February 1999, Monterey, Calif, USA 157-166.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Centre for High Performance Embedded Systems (CHiPES), School of Computer Engineering, Nanyang Technology University, 639798, Singapore

    Timothy F Oliver & Douglas L Maskell

Authors
  1. Timothy F Oliver
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Douglas L Maskell
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Timothy F Oliver.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and Permissions

About this article

Cite this article

Oliver, T.F., Maskell, D.L. Prerouted FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System. J Embedded Systems 2007, 041867 (2007). https://doi.org/10.1155/2007/41867

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1155/2007/41867

Keywords

  • Encapsulation
  • Design Flow
  • System Construction
  • Dynamic Reconfigurable
  • Reconfigurable System