Formal Methods for Scheduling of Latency-Insensitive Designs
EURASIP Journal on Embedded Systems volume 2007, Article number: 039161 (2007)
Latency-insensitive design (LID) theory was invented to deal with SoC timing closure issues, by allowing arbitrary fixed integer latencies on long global wires. Latencies are coped with using a resynchronization protocol that performs dynamic scheduling of data transportation. Functional behavior is preserved. This dynamic scheduling is implemented using specific synchronous hardware elements: relay-stations (RS) and shell-wrappers (SW). Our first goal is to provide a formal modeling of RS and SW, that can be then formally verified. As turns out, resulting behavior is k-periodic, thus amenable to static scheduling. Our second goal is to provide formal hardware modeling here also. It initially performs throughput equalization, adding integer latencies wherever possible; residual cases require introduction of fractional registers (FRs) at specific locations. Benchmark results are presented, run on our Kpassa tool implementation.
Carloni LP, McMillan KL, Sangiovanni-Vincentelli AL: Theory of latency-insensitive design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2001,20(9):1059-1076. 10.1109/43.945302
Carloni LP, McMillan KL, Saldanha A, Sangiovanni-Vincentelli AL: A methodology for correct-by-construction latency insensitive design. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '99), November 1999, San Jose, Calif, USA 309-315.
Carloni LP, Sangiovanni-Vincentelli AL: Performance analysis and optimization of latency insensitive systems. Proceedings of the 37th Conference on Design automation (DAC '00), June 2000, Los Angeles, Calif, USA 361-367.
Chelcea T, Nowick SM: Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. Proceedings of the 38th conference on Design automation (DAC '01), June 2001, Las Vegas, Nev, USA 21-26.
Chakraborty A, Greenstreet MR: A minimalist source-synchronous interface. Proceedings of the 15th Annual IEEE International ASIC/SOC Conference, September 2002, Rochester, NY, USA 443-447.
Commoner F, Holt AW, Even S, Pnueli A: Marked directed graphs. Journal of Computer and System Sciences 1971,5(5):511-523. 10.1016/S0022-0000(71)80013-2
Ramchandani C: Analysis of asynchronous concurrent systems by timed Petri nets, Ph.D. thesis. MIT, Cambridge, Mass, USA; 1973.
Carlier J, Chrétienne P: Problème d'ordonnancement: modélisation, complexité, algorithmes. Masson, Paris, France; 1988.
Baccelli F, Cohen G, Olsder GJ, Quadrat J-P: Synchronization and Linearity: An Algebra for Discrete Event Systems. John Wiley & Sons, New York, NY, USA; 1992.
van Dongen V, Gao GR, Ning Q: A polynomial time method for optimal software pipelining. In Proceedings of the 2nd Joint International Conference on Vector and Parallel Processing (CONPAR '92), September 1992, Lyon, France. Springer; 613-624.
Boyer F-R, Aboulhamid EM, Savaria Y, Boyer M: Optimal design of synchronous circuits using software pipelining techniques. Proceedings of IEEE International Conference on Computer Design (ICCD '98), October 1998, Austin, Tex, USA 62-67.
Casu MR, Macchiarulo L: A new approach to latency insensitive design. In Proceedings of the 41st Annual Conference on Design Automation (DAC '04), June 2004, San Diego, Calif, USA. ACM Press; 576-581.
Cohen A, Duranton M, Eisenbeis C, Pagetti C, Plateau F, Pouzet M: N -synchronous Kahn networks: a relaxed model of synchrony for real-time systems. In Proceedings of the 33rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (POPL '06), January 2006, Charleston, South Carolina, USA. ACM Press; 180-193.
Boucaron J, Millo J-V, de Simone R: Another glance at relay stations in latency-insensitive design. Electronic Notes in Theoretical Computer Science 2006,146(2):41-59. 10.1016/j.entcs.2005.05.035
Casu MR, Macchiarulo L: A detailed implementation of latency insensitive protocols. Proceedings of Formal Methods for Globally Asyncronous Locally Syncronous Architectures, September 2003, Pisa, Italy 94-103.
Benveniste A, Caspi P, Edwards SA, Halbwachs N, Le Guernic P, de Simone R: The synchronous languages 12 years later. Proceedings of the IEEE 2003,91(1):64-83. 10.1109/JPROC.2002.805826
Yakovlev AV, Koelmans AM, Lavagno L: High-level modeling and design of asynchronous interface logic. IEEE Design and Test of Computers 1995,12(1):32-40. 10.1109/54.350688
Casu MR, Macchiarulo L: Floorplanning for throughput. In Proceedings of the International Symposium on Physical Design (ISPD '04), April 2004, Phoenix, Ariz, USA. ACM Press; 62-69.
André C: Representation and analysis of reactive behaviors: a synchronous approach. Proceedings of the IMAC Multiconference on Computational Engineering in Systems Applications (CESA '96), July 1996, Lille, France 19-29.
Dasdan A: Experimental analysis of the fastest optimum cycle ratio and mean algorithms. ACM Transactions on Design Automation of Electronic Systems 2004,9(4):385-418. 10.1145/1027084.1027085
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Boucaron, J., de Simone, R. & Millo, JV. Formal Methods for Scheduling of Latency-Insensitive Designs. J Embedded Systems 2007, 039161 (2007). https://doi.org/10.1155/2007/39161
- Formal Method
- Electronic Circuit
- Timing Closure
- Dynamic Schedule
- Functional Behavior