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Formal Methods for Scheduling of Latency-Insensitive Designs

Abstract

Latency-insensitive design (LID) theory was invented to deal with SoC timing closure issues, by allowing arbitrary fixed integer latencies on long global wires. Latencies are coped with using a resynchronization protocol that performs dynamic scheduling of data transportation. Functional behavior is preserved. This dynamic scheduling is implemented using specific synchronous hardware elements: relay-stations (RS) and shell-wrappers (SW). Our first goal is to provide a formal modeling of RS and SW, that can be then formally verified. As turns out, resulting behavior is k-periodic, thus amenable to static scheduling. Our second goal is to provide formal hardware modeling here also. It initially performs throughput equalization, adding integer latencies wherever possible; residual cases require introduction of fractional registers (FRs) at specific locations. Benchmark results are presented, run on our Kpassa tool implementation.

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Correspondence to Julien Boucaron.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Boucaron, J., de Simone, R. & Millo, J. Formal Methods for Scheduling of Latency-Insensitive Designs. J Embedded Systems 2007, 039161 (2007). https://doi.org/10.1155/2007/39161

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Keywords

  • Formal Method
  • Electronic Circuit
  • Timing Closure
  • Dynamic Schedule
  • Functional Behavior