Skip to main content
EURASIP Journal on Embedded Systems
Download PDF

Geometry Unit for Analysis of Warped Image Features on Programmable Chips

EURASIP Journal on Embedded Systems volume 2007, Article number: 037317 (2007) Cite this article

Abstract

Among many constraints applicable for embedded visions systems in industrial applications, desired processing performance is a determining factor of system costs. For technically and economically successful solutions, it is essential to match algorithms and architecture. High-end field programmable gate arrays open the perspective to vision systems on a programmable chip, leading to reduced size and higher performance. The architecture proposed in our previous publications in 2004 and 2006 is based on reusable building blocks. This paper continues with a particular building block for backward warping and interpolation of arbitrary shaped image regions, which can be used for many image processing tasks, including image statistics, projections, and template matching. The architecture is discussed and a typical application for template matching is presented. The suggested unit serves as universal basis for high-level image processing implemented on programmable chips, which enables a new generation of integrated high performance embedded vision systems maintaining reasonable system costs due to design reuse of basic units.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20]

References

  1. Rössler P, Eckel C, Nachtnebel H, Fürtler J, Cadek G: FPGA-Design für ein Hochleistungs-bildverarbeitungssystem. Proceedings of the Austrian National Conference on Microelectronics (Austrochip '04), October 2004, Villach, Austria 83-88.

    Google Scholar 

  2. Fürtler J, Brodersen J, Rössler P, et al.: Architecture for hardware driven image inspection based on FPGAs. Real-Time Image Processing, January 2006, San Jose, Calif, USA, Proceedings of SPIE 6063: 105-113.

    Google Scholar 

  3. Fürtler J, Rössler P, Brodersen J, et al.: Design considerations for scalable high-performance vision systems embedded in industrial print inspection machines. to appear in EURASIP Journal on Embedded Systems

  4. Salcic Z, Smailagic A: Digital Systems Design and Prototyping Using Field Programmable Logic and Hardware Description Languages. Kluwer Academic, Boston, Mass, USA; 2000.

    MATH  Google Scholar 

  5. Davies ER: Machine Vision. Morgan Kaufmann, San Francisco, Calif, USA; 2005.

    Google Scholar 

  6. Penz H, Bajla I, Mayer KJ, Krattenthaler W: High-speed template matching with point correlation in image pyramids. Diagnostic Imaging Technologies and Industrial Applications, June 1999, Munich, Germany, Proceedings of SPIE 3827: 85-94.

    Article  Google Scholar 

  7. Lewis JP: Fast normalized cross-correlation. Vision Interface, June 1995, Quebec, Canada 120-123.

    Google Scholar 

  8. Aschwanden P, Guggenbühl W: Experimental results from a comparative study on correlation-type regi ion algorithms. In Robust Computer Vision: Quality of Vision Algorithms. Edited by: Förstner W, Ruwiedel S. Wichmann, Karlsruhe, Germany; 1992:268-289.

    Google Scholar 

  9. Krattenthaler W, Mayer KJ: Point correlation: a reduced-cost template matching technique. Proceedings of the 1st IEEE International Conference on Image Processing (ICIP '94), November 1994, Austin, Tex, USA 1: 208-212.

    Article  Google Scholar 

  10. Krattenthaler W, Mayer KJ: Point correlation: a new approach for high-speed template matching. Proceedings of DAGM/OAGM Conference, September 1994, Vienna, Austria 642-649.

    Google Scholar 

  11. Jähne B: Digital Image Processing. Springer, New York, NY, USA; 1991.

    Google Scholar 

  12. Penz H, Bajla I, Vrabl A, Krattenthaler W, Mayer KJ: Fast real-time recognition and quality inspection of printed characters via point-correlation. Real-Time Imaging V, January 2001, San Jose, Calif, USA, Proceedings of SPIE 4303: 127-137.

    Article  Google Scholar 

  13. Fürtler J, Krattenthaler W, Mayer KJ, Penz H, Vrabl A: SIS-Stamp: an integrated inspection system for sheet prints in stamp printing application. Computers in Industry 2005,56(8-9):958-974. 10.1016/j.compind.2005.05.019

    Article  Google Scholar 

  14. DDR SDRAM Controller MegaCore Function User Guide document version 1.2.0 rev 1, Altera, San Jose, Calif, USA, March 2003

  15. Stratix Device Handbook S5V1-3.1 and S5V2-3.1, Altera, San Jose, Calif, USA

  16. Stratix II Device Handbook SII5v1-3.1 and SII5v2-3.1, Altera, San Jose, Calif, USA

  17. Virtex-II Platform FPGAs: Complete Datasheet DS 031 (v3.4), Xilinx, San Jose, Calif, USA

  18. Virtex-4 User Guide UG 07 (v1.5) and UG073 (v2.1), Xilinx, San Jose, Calif, USA

  19. Fürtler J, Mayer KJ, Krattenthaler W, Bajla I: SPOT—development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing. Real-Time Imaging 2003,9(6):387-399. 10.1016/j.rti.2003.09.017

    Article  Google Scholar 

  20. Nölle M, Penz H, Rubik M, Mayer KJ, Holländer I, Granec R: Dagobert—a new coin recognition and sorting system. Proceedings of the 7th International Conference on Digital Image Computing—Techniques and Applications (DICTA '03), December 2003, Sydney, Australia 1: 329-338.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Business Unit of High Performance Image Processing, Austrian Research Centers Gmbh-ARC, Seibersdorf, 2444, Austria

    Johannes Fürtler, Konrad J Mayer & Jörg Brodersen

  2. Oregano Systems - Design and Consulting GmbH, Phorusgasse 8, Vienna, 1040, Austria

    Christian Eckel & Gerhard Cadek

  3. Institute of Computer Technology, Vienna University of Technology, Gußhausstraße 27-29/E384, Vienna, 1040, Austria

    Herbert Nachtnebel

Authors
  1. Johannes Fürtler
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Konrad J Mayer
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Christian Eckel
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Jörg Brodersen
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Herbert Nachtnebel
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Gerhard Cadek
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Johannes Fürtler.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and Permissions

About this article

Cite this article

Fürtler, J., Mayer, K.J., Eckel, C. et al. Geometry Unit for Analysis of Warped Image Features on Programmable Chips. J Embedded Systems 2007, 037317 (2007). https://doi.org/10.1155/2007/37317

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1155/2007/37317

Keywords

  • Field Programmable Gate Array
  • Image Region
  • Electronic Circuit
  • Processing Task
  • System Cost