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Geometry Unit for Analysis of Warped Image Features on Programmable Chips

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Abstract

Among many constraints applicable for embedded visions systems in industrial applications, desired processing performance is a determining factor of system costs. For technically and economically successful solutions, it is essential to match algorithms and architecture. High-end field programmable gate arrays open the perspective to vision systems on a programmable chip, leading to reduced size and higher performance. The architecture proposed in our previous publications in 2004 and 2006 is based on reusable building blocks. This paper continues with a particular building block for backward warping and interpolation of arbitrary shaped image regions, which can be used for many image processing tasks, including image statistics, projections, and template matching. The architecture is discussed and a typical application for template matching is presented. The suggested unit serves as universal basis for high-level image processing implemented on programmable chips, which enables a new generation of integrated high performance embedded vision systems maintaining reasonable system costs due to design reuse of basic units.

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Correspondence to Johannes Fürtler.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Keywords

  • Field Programmable Gate Array
  • Image Region
  • Electronic Circuit
  • Processing Task
  • System Cost