Skip to main content

Energy-Efficient Acceleration of MPEG-4 Compression Tools

Abstract

We propose novel hardware accelerator architectures for the most computationally demanding algorithms of the MPEG-4 video compression standard-motion estimation, binary motion estimation (for shape coding), and the forward/inverse discrete cosine transforms (incorporating shape adaptive modes). These accelerators have been designed using general low-energy design philosophies at the algorithmic/architectural abstraction levels. The themes of these philosophies are avoiding waste and trading area/performance for power and energy gains. Each core has been synthesised targeting TSMC 0.09 μ m TCBN90LP technology, and the experimental results presented in this paper show that the proposed cores improve upon the prior art.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37]

References

  1. Chai D, Ngan KN: Face segmentation using skin-color map in videophone applications. IEEE Transactions on Circuits and Systems for Video Technology 1999,9(4):551-564. 10.1109/76.767122

    Article  Google Scholar 

  2. MPEG-4: Information Technology—Coding of Audio Visual Objects—Part 2: Visual, ISO/IEC 14496-2, ISO/IEC Std., Rev. Amendment 1, July 2000

  3. Sikora T: The MPEG-4 video standard verification model. IEEE Transactions on Circuits and Systems for Video Technology 1997,7(1):19-31. 10.1109/76.554415

    Article  Google Scholar 

  4. Tseng P-C, Chang Y-C, Huang Y-W, Fang H-C, Huang C-T, Chen L-G: Advances in hardware architectures for image and video coding—a survey. Proceedings of the IEEE 2005,93(1):184-197.

    Article  Google Scholar 

  5. Chang H-C, Wang Y-C, Hsu M-Y, Chen L-G: Efficient algorithms and architectures for MPEG-4 object-based video coding. Proceedings of IEEE Workshop on Signal Processing Systems (SiPS '00), October 2000, Lafayette, La, USA 13-22.

    Google Scholar 

  6. Kuhn P: Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation. 1st edition. Kluwer Academic, Dordrecht, The Netherlands; 1999.

    MATH  Book  Google Scholar 

  7. Landman P: Low-power architectural design methodologies, Ph.D. dissertation. http://bwrc.eecs.berkeley.edu/Publications/1994/theses/lw_pwr_arch_des_meth_Landman/Landman94.pdf

  8. Yeap GK: Practical Low Power Digital VLSI Design. 1st edition. Kluwer Academic, Dordrecht, The Netherlands; 1998.

    Book  Google Scholar 

  9. Kinane A: Energy efficient hardware acceleration of multimedia processing tools, Ph.D. dissertation. http://www.eeng.dcu.ie/~kinanea/thesis/kinane_final.pdf

  10. Cheng S-C, Hang H-M: A comparison of block-matching algorithms mapped to systolic-array implementation. IEEE Transactions on Circuits and Systems for Video Technology 1997,7(5):741-757. 10.1109/76.633491

    Article  Google Scholar 

  11. Chan E, Panchanathan S: Motion estimation architecture for video compression. IEEE Transactions on Consumer Electronics 1993,39(3):292-297. 10.1109/30.234596

    Article  Google Scholar 

  12. Cheung C-K, Po L-M: Normalized partial distortion search algorithm for block motion estimation. IEEE Transactions on Circuits and Systems for Video Technology 2000,10(3):417-422. 10.1109/76.836286

    Article  Google Scholar 

  13. Lai Y-K, Chen L-G: A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm. IEEE Transactions on Circuits and Systems for Video Technology 1998,8(2):124-127. 10.1109/76.664095

    MathSciNet  Article  Google Scholar 

  14. Jehng Y-S, Chen L-G, Chiueh T-D: An efficient and simple VLSI tree architecture for motion estimation algorithms. IEEE Transactions on Signal Processing 1993,41(2):889-900. 10.1109/78.193224

    Article  Google Scholar 

  15. Nakayama H, Yoshitake T, Komazaki H, et al.: A MPEG-4 video LSI with an error-resilient codec core based on a fast motion estimation algorithm. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '02), February 2002, San Francisco, Calif, USA 2: 296.

    Google Scholar 

  16. Do VL, Yun KY: A low-power VLSI architecture for full-search block-matching motion estimation. IEEE Transactions on Circuits and Systems for Video Technology 1998,8(4):393-398. 10.1109/76.709406

    Article  Google Scholar 

  17. Takahashi M, Nishikawa T, Hamada M, et al.: A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. IEEE Journal of Solid-State Circuits 2000,35(11):1713-1721. 10.1109/4.881219

    Article  Google Scholar 

  18. Chang N, Kim K, Lee HG: Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2002,10(2):146-154.

    Article  Google Scholar 

  19. Brady N: MPEG-4 standardized methods for the compression of arbitrarily shaped video objects. IEEE Transactions on Circuits and Systems for Video Technology 1999,9(8):1170-1189. 10.1109/76.809154

    Article  Google Scholar 

  20. Yu D, Jang SK, Ra JB: Fast motion estimation for shape coding in MPEG-4. IEEE Transactions on Circuits and Systems for Video Technology 2003,13(4):358-363. 10.1109/TCSVT.2003.811430

    Article  Google Scholar 

  21. Panusopone K, Chen X: A fast motion estimation method for MPEG-4 arbitrarily shaped objects. Proceedings of IEEE International Conference on Image Processing (ICIP '00), September 2000, Vancouver, BC, Canada 3: 624-627.

    Google Scholar 

  22. Tsai T-H, Chen C-P: A fast binary motion estimation algorithm for MPEG-4 shape coding. IEEE Transactions on Circuits and Systems for Video Technology 2004,14(6):908-913. 10.1109/TCSVT.2004.828318

    Article  Google Scholar 

  23. Lee K-B, Chin H-Y, Chang NY-C, Hsu H-J, Jen C-W: A memory-efficient binary motion estimation architecture for MPEG-4 shape coding. Proceedings of the 16th European Conference on Circuit Theory and Design (ECCTD '03), September 2003, Cracow, Poland 2: 93-96.

    Google Scholar 

  24. Lee K-B, Chin H-Y, Chang NY-C, Hsu H-C, Jen C-W: Optimal frame memory and data transfer scheme for MPEG-4 shape coding. IEEE Transactions on Consumer Electronics 2004,50(1):342-348. 10.1109/TCE.2004.1277883

    Article  Google Scholar 

  25. Natarajan B, Bhaskaran V, Konstantinides K: Low-complexity block-based motion estimation via one-bit transforms. IEEE Transactions on Circuits and Systems for Video Technology 1997,7(4):702-706. 10.1109/76.611181

    Article  Google Scholar 

  26. Larkin D, Muresan V, O'Connor N: A low complexity hardware architecture for motion estimation. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '06), May 2006, Kos, Greece 2677-2680.

    Google Scholar 

  27. Mizuki MM, Desai UY, Masaki I, Chandrakasan A: A binary block matching architecture with reduced power consumption and silicon area requirement. Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '96), May 1996, Atlanta, Ga, USA 6: 3248-3251.

    Google Scholar 

  28. Sikora T, Makai B: Shape-adaptive DCT for generic coding of video. IEEE Transactions on Circuits and Systems for Video Technology 1995,5(1):59-62. 10.1109/76.350781

    Article  Google Scholar 

  29. Le T, Glesner M: Flexible architectures for DCT of variable-length targeting shape-adaptive transform. IEEE Transactions on Circuits and Systems for Video Technology 2000,10(8):1489-1495. 10.1109/76.889058

    Article  Google Scholar 

  30. Tseng P-C, Haung C-T, Chen L-G: Reconfigurable discrete cosine transform processor for object-based video signal processing. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '04), May 2004, Vancouver, BC, Canada 2: 353-356.

    Google Scholar 

  31. Chen K-H, Guo J-I, Wang J-S, Yeh C-W, Chen T-F: A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG-4 shape-adaptive transforms. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '04), May 2004, Vancouver, BC, Canada 2: 141-144.

    Google Scholar 

  32. Chen K-H, Guo J-I, Wang J-S, Yeh C-W, Chen J-W: An energy-aware IP core design for the variable-length DCT/IDCT targeting at MPEG-4 shape-adaptive transforms. IEEE Transactions on Circuits and Systems for Video Technology 2005,15(5):704-715.

    Article  Google Scholar 

  33. Lee K-B, Hsu H-C, Jen C-W: A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '04), May 2004, Vancouver, BC, Canada 2: 777-780.

    Google Scholar 

  34. Kinane A, Muresan V, O'Connor N, Murphy N, Marlow S: Energy-efficient hardware architecture for variable N-point 1D DCT. Proceedings of International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS '04), September 2004, Santorini, Greece 780-788.

    Google Scholar 

  35. Potkonjak M, Srivastava MB, Chandrakasan AP: Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1996,15(2):151-165. 10.1109/43.486662

    Article  Google Scholar 

  36. Koren I: Computer Arithmetic Algorithms. 2nd edition. A. K. Peters, Natick, Mass, USA; 2002.

    MATH  Google Scholar 

  37. Hsu H-C, Lee K-B, Chang NY-C, Chang T-S: An MPEG-4 shape-adaptive inverse DCT with zero skipping and auto-aligned transpose memory. Proceedings of IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS '04), December 2004, Tainan, Taiwan 2: 773-776.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Andrew Kinane.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and Permissions

About this article

Cite this article

Kinane, A., Larkin, D. & O'Connor, N. Energy-Efficient Acceleration of MPEG-4 Compression Tools. J Embedded Systems 2007, 028735 (2007). https://doi.org/10.1155/2007/28735

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1155/2007/28735

Keywords

  • Control Structure
  • Motion Estimation
  • Energy Gain
  • Electronic Circuit
  • Abstraction Level