Skip to main content
EURASIP Journal on Embedded Systems
Download PDF
  • Research Article
  • Open access
  • Published:

Communication-Oriented Design Space Exploration for Reconfigurable Architectures

EURASIP Journal on Embedded Systems volume 2007, Article number: 023496 (2007) Cite this article

Abstract

Many academic works in computer engineering focus on reconfigurable architectures and associated tools. Fine-grain architectures, field programmable gate arrays (FPGAs), are the most well-known structures of reconfigurable hardware. Dedicated tools (generic or specific) allow for the exploration of their design space to choose the best architecture characteristics and/or to explore the application characteristics. The aim is to increase the synergy between the application and the architecture in order to get the best performance. However, there is no generic tool to perform such an exploration for coarse-grain or heterogeneous-grain architectures, just a small number of very specific tools are able to explore a limited set of architectures. To address this major lack, in this paper we propose a new design space exploration approach adapted to fine- and coarse-grain granularities. Our approach combines algorithmic and architecture explorations. It relies on an automatic estimation tool which computes the communication hierarchical distribution and the architectural processing resources use rate for the architecture under exploration. Such an approach forwards the rapid definition of efficient reconfigurable architectures dedicated to one or several applications.

[1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33]

References

  1. Tredennick N, Shimamoto B: The rise of reconfigurable systems. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '03), June 2003, Las Vegas, Nev, USA 3-12.

    Google Scholar 

  2. Hartenstein R: A decade of reconfigurable computing: a visionary retrospective. Proceedings of Conference and Exhibition on Design, Automation and Test in Europe (DATE '01), March 2001, Munich, Germany 642-649.

    Google Scholar 

  3. Schaumont P, Verbauwhede I, Keutzer K, Sarrafzadeh M: A quick safari through the reconfiguration jungle. Proceedings of the 38th Design Automation Conference (DAC '01), June 2001, Las Vegas, Nev, USA 172-177.

    Google Scholar 

  4. Pimentel AD, Hertzberger LO, Lieverse P, van der Wolf P, Deprettere EdF: Exploring embedded-systems architectures with artemis. Computer 2001,34(11):57-63. 10.1109/2.963445

    Article  Google Scholar 

  5. Bossuet L: Exploration de l'espace de conception des architectures reconfigurables, Ph.D. thesis. Université de Bretagne Sud, Vannes, France; 2004.

    Google Scholar 

  6. Gries M: Methods for evaluating covering the design space during early design development. In Technical Memorandum MO3/32. Electronics Research Laboratory, University of California, Berkeley, Calif, USA; 2003.

    Google Scholar 

  7. Betz V, Rose J: VPR: a new packing, placement and routing tool for FPGA research. Proceedings of the 7th International Workshop on Field Programmable Logic (FPL '97), September 1997, Oxford, UK 213-222.

    Google Scholar 

  8. Ahmed E, Rose J: The effect of LUT and cluster size on deep-submicron FPGA performance and density. Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '00), February 2000, Moterey, Calif, USA 3-12.

    Google Scholar 

  9. Wilton SJE, Rose J, Vranesic ZG: The memory/logic interface in FPGA's with large embedded memory arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1999,7(1):80-91. 10.1109/92.748203

    Article  Google Scholar 

  10. Lagadec L: Abstraction, modélisation et outils de CAO pour les circuits intégrés reconfigurables, Ph.D. thesis. Université de Rennes1, Rennes, France; 2000.

    Google Scholar 

  11. Choi S, Jang JW, Mohanty S, Prasanna VK: Domain-specific modeling for rapid system-level energy estimation of reconfigurable architectures. Proceedings of International Conference of Engineering of Reconfigurable Systems and Algorithms (ERSA '02), June 2002, Las Vegas, Nev, USA

    Google Scholar 

  12. Enzler R, Jeger T, Cottet D, Tröster G: High-level area and performance estimation of hardware building blocks on FPGAs. Proceedings of the the Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications (FPL '00), August 2000, Villach, Austria 525-534.

    Chapter  Google Scholar 

  13. Moritz CA, Yeung D, Agarwal A: Exploring optimal cost-performance designs for Raw microprocessors. Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '98), April 1998, Napa Valley, Calif, USA 12-27.

    Chapter  Google Scholar 

  14. Nadelginder U: Coarse-grain reconfigurable architecture design space architecture exploration, Ph.D. thesis. University of Kaiserslautern, Kaiserslautern, Germany; 2001.

    Google Scholar 

  15. Kress R: A fast reconfigurable ALU for xputers, Ph.D. thesis. University of Kaiserslautern, Kaiserslautern, Germany; 1996.

    Google Scholar 

  16. Bossuet L, Gogniat G, Philippe J-L: Generic design space exploration for reconfigurable architectures. Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS '05), April 2005, Denver, Colo, USA 163.

    Chapter  Google Scholar 

  17. Design Trotter Project: http://web.univ-ubs.fr/lester/~diguet/Design-TrotterPage.html

  18. Diguet JP, Gogniat G, Danielo P, Auguin M, Philippe J-L: The SPF model. Proceedings of Forum on Design Language (FDL '00), September 2000, Tübingen, Germany

    Google Scholar 

  19. Le Moullec Y, Koch P, Diguet JP, Philippe J-L: Design trotter: building and selecting architectures for embedded multimedia applications. Proceedings of IEEE International Symposium on Consumer Electronics (ISCE '03), December 2003, Sydney, Australia

    Google Scholar 

  20. Le Moullec Y, Diguet JP, Gourdeaux T, Philippe J-L: Design trotter: system-level dynamic estimation task a 1st step towards platform architecture selection. Journal of Embedded Computing 2005,1(4):565-586.

    Google Scholar 

  21. Bossuet L, Gogniat G, Philippe J-L: Fast design space exploration method for reconfigurable architectures. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '03), June 2003, Las Vegas, Nev, USA 65-71.

    Google Scholar 

  22. Mudge T: Power: a first-class architectural design constraint. Computer 2001,34(4):52-58. 10.1109/2.917539

    Article  Google Scholar 

  23. Rouxel S: Caractérisation de l'impact du routage sur les performances (vitesse et consommation de puissance) d'un FPGA, M.S. thesis. Université de Bretagne Sud, Lorient, France; 2003.

    Google Scholar 

  24. Elleouet D: Caractérisation et modélisation de la consommation de puissance des mémoires sur FPGA, M.S. thesis. Université de Bretagne Sud, Lorient, France; 2003.

    Google Scholar 

  25. Garcia A, Burleson W, Danger J-L: Power modelling in field programmable gate arrays (FPGA). Proceeding of the 9th International Workshop on Field Programmable Logic and Applications (FPL '99), August-September 1999, Glasgow, Scotland 396-404.

    Chapter  Google Scholar 

  26. George V, Zhang H, Rabaey J: The design of a low energy FPGA. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '99), August 1999, San Diego, Calif, USA 188-193.

    Google Scholar 

  27. Kusse E, Rabaey JM: Low-energy embedded FPGA structures. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '98), August 1998, Monterey, Calif, USA 155-160.

    Google Scholar 

  28. Shang L, Kaviani AS, Bathala K: Dynamic power consumption in virtexTM -II FPGA family. Proceedings of the 10th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '02), February 2002, Monterey, Calif, USA 157-164.

    Google Scholar 

  29. Poon KKW, Yan A, Wilton SJE: A flexible power model for FPGAs. Proceeding of the 12th International Conference on Field-Programmable Logic and Applications (FPL '02), September 2002, Montpellier, France 312-321.

    Google Scholar 

  30. Zhang H, Wan M, George V, Rabaey J: Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs. Proceedings of the IEEE Computer Society Workshop on VLSI (WVLSI '99), April 1999, Orlando, Fla, USA 2.

    Google Scholar 

  31. CEA. Intelligent Camera—3D Methodology. http://www-list.cea.fr/fr/programmes/systemes_embarques/docs/ICAM_internet_list_v0.pdf

  32. Mallat SG, Zhang Z: Matching pursuits with time-frequency dictionaries. IEEE Transactions on Signal Processing 1993,41(12):3397-3415. 10.1109/78.258082

    Article  MATH  Google Scholar 

  33. MPEG2, http://www.mpeg2.de

Download references

Author information

Authors and Affiliations

  1. Laboratoire de l'Intégration du Matériau au Système, CNRS UMR5218, Université de Bordeaux 1, Talence, Cedex 33405, France

    Lilian Bossuet

  2. Laboratory of Electronic and Real Time Systems (LESTER), CNRS FRE2734, University of South Brittany, Lorient, Cedex 56321, France

    Guy Gogniat & Jean-Luc Philippe

Authors
  1. Lilian Bossuet
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Guy Gogniat
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jean-Luc Philippe
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Lilian Bossuet.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License (https://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Reprints and permissions

About this article

Cite this article

Bossuet, L., Gogniat, G. & Philippe, JL. Communication-Oriented Design Space Exploration for Reconfigurable Architectures. J Embedded Systems 2007, 023496 (2007). https://doi.org/10.1155/2007/23496

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1155/2007/23496

Keywords