Tredennick N, Shimamoto B: The rise of reconfigurable systems. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '03), June 2003, Las Vegas, Nev, USA 3-12.
Google Scholar
Hartenstein R: A decade of reconfigurable computing: a visionary retrospective. Proceedings of Conference and Exhibition on Design, Automation and Test in Europe (DATE '01), March 2001, Munich, Germany 642-649.
Google Scholar
Schaumont P, Verbauwhede I, Keutzer K, Sarrafzadeh M: A quick safari through the reconfiguration jungle. Proceedings of the 38th Design Automation Conference (DAC '01), June 2001, Las Vegas, Nev, USA 172-177.
Google Scholar
Pimentel AD, Hertzberger LO, Lieverse P, van der Wolf P, Deprettere EdF: Exploring embedded-systems architectures with artemis. Computer 2001,34(11):57-63. 10.1109/2.963445
Article
Google Scholar
Bossuet L: Exploration de l'espace de conception des architectures reconfigurables, Ph.D. thesis. Université de Bretagne Sud, Vannes, France; 2004.
Google Scholar
Gries M: Methods for evaluating covering the design space during early design development. In Technical Memorandum MO3/32. Electronics Research Laboratory, University of California, Berkeley, Calif, USA; 2003.
Google Scholar
Betz V, Rose J: VPR: a new packing, placement and routing tool for FPGA research. Proceedings of the 7th International Workshop on Field Programmable Logic (FPL '97), September 1997, Oxford, UK 213-222.
Google Scholar
Ahmed E, Rose J: The effect of LUT and cluster size on deep-submicron FPGA performance and density. Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '00), February 2000, Moterey, Calif, USA 3-12.
Google Scholar
Wilton SJE, Rose J, Vranesic ZG: The memory/logic interface in FPGA's with large embedded memory arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1999,7(1):80-91. 10.1109/92.748203
Article
Google Scholar
Lagadec L: Abstraction, modélisation et outils de CAO pour les circuits intégrés reconfigurables, Ph.D. thesis. Université de Rennes1, Rennes, France; 2000.
Google Scholar
Choi S, Jang JW, Mohanty S, Prasanna VK: Domain-specific modeling for rapid system-level energy estimation of reconfigurable architectures. Proceedings of International Conference of Engineering of Reconfigurable Systems and Algorithms (ERSA '02), June 2002, Las Vegas, Nev, USA
Google Scholar
Enzler R, Jeger T, Cottet D, Tröster G: High-level area and performance estimation of hardware building blocks on FPGAs. Proceedings of the the Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications (FPL '00), August 2000, Villach, Austria 525-534.
Chapter
Google Scholar
Moritz CA, Yeung D, Agarwal A: Exploring optimal cost-performance designs for Raw microprocessors. Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '98), April 1998, Napa Valley, Calif, USA 12-27.
Chapter
Google Scholar
Nadelginder U: Coarse-grain reconfigurable architecture design space architecture exploration, Ph.D. thesis. University of Kaiserslautern, Kaiserslautern, Germany; 2001.
Google Scholar
Kress R: A fast reconfigurable ALU for xputers, Ph.D. thesis. University of Kaiserslautern, Kaiserslautern, Germany; 1996.
Google Scholar
Bossuet L, Gogniat G, Philippe J-L: Generic design space exploration for reconfigurable architectures. Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS '05), April 2005, Denver, Colo, USA 163.
Chapter
Google Scholar
Design Trotter Project: http://web.univ-ubs.fr/lester/~diguet/Design-TrotterPage.html
Diguet JP, Gogniat G, Danielo P, Auguin M, Philippe J-L: The SPF model. Proceedings of Forum on Design Language (FDL '00), September 2000, Tübingen, Germany
Google Scholar
Le Moullec Y, Koch P, Diguet JP, Philippe J-L: Design trotter: building and selecting architectures for embedded multimedia applications. Proceedings of IEEE International Symposium on Consumer Electronics (ISCE '03), December 2003, Sydney, Australia
Google Scholar
Le Moullec Y, Diguet JP, Gourdeaux T, Philippe J-L: Design trotter: system-level dynamic estimation task a 1st step towards platform architecture selection. Journal of Embedded Computing 2005,1(4):565-586.
Google Scholar
Bossuet L, Gogniat G, Philippe J-L: Fast design space exploration method for reconfigurable architectures. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '03), June 2003, Las Vegas, Nev, USA 65-71.
Google Scholar
Mudge T: Power: a first-class architectural design constraint. Computer 2001,34(4):52-58. 10.1109/2.917539
Article
Google Scholar
Rouxel S: Caractérisation de l'impact du routage sur les performances (vitesse et consommation de puissance) d'un FPGA, M.S. thesis. Université de Bretagne Sud, Lorient, France; 2003.
Google Scholar
Elleouet D: Caractérisation et modélisation de la consommation de puissance des mémoires sur FPGA, M.S. thesis. Université de Bretagne Sud, Lorient, France; 2003.
Google Scholar
Garcia A, Burleson W, Danger J-L: Power modelling in field programmable gate arrays (FPGA). Proceeding of the 9th International Workshop on Field Programmable Logic and Applications (FPL '99), August-September 1999, Glasgow, Scotland 396-404.
Chapter
Google Scholar
George V, Zhang H, Rabaey J: The design of a low energy FPGA. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '99), August 1999, San Diego, Calif, USA 188-193.
Google Scholar
Kusse E, Rabaey JM: Low-energy embedded FPGA structures. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '98), August 1998, Monterey, Calif, USA 155-160.
Google Scholar
Shang L, Kaviani AS, Bathala K: Dynamic power consumption in virtexTM
-II FPGA family. Proceedings of the 10th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '02), February 2002, Monterey, Calif, USA 157-164.
Google Scholar
Poon KKW, Yan A, Wilton SJE: A flexible power model for FPGAs. Proceeding of the 12th International Conference on Field-Programmable Logic and Applications (FPL '02), September 2002, Montpellier, France 312-321.
Google Scholar
Zhang H, Wan M, George V, Rabaey J: Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs. Proceedings of the IEEE Computer Society Workshop on VLSI (WVLSI '99), April 1999, Orlando, Fla, USA 2.
Google Scholar
CEA. Intelligent Camera—3D Methodology. http://www-list.cea.fr/fr/programmes/systemes_embarques/docs/ICAM_internet_list_v0.pdf
Mallat SG, Zhang Z: Matching pursuits with time-frequency dictionaries. IEEE Transactions on Signal Processing 1993,41(12):3397-3415. 10.1109/78.258082
Article
MATH
Google Scholar
MPEG2, http://www.mpeg2.de