Table 4 Specification of CMP configurations evaluated in this work
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
Component | Description |
|---|---|
Number of cores | Experiment 1, 16, 4 × 4 mesh Experiment 2, 64, 8 × 8 mesh |
Core configuration | Alpha21164, 3Â GHz, area 3.5Â mm2, 32Â nm |
L1 cache | SRAM, 4 way, 32B line, size 32Â KB private per each core |
L2/L3/L4 caches | L2: SRAM, L3: SRAM, L4: SRAM (baseline) L2: SRAM, L3: eDRAM, L4: STT-RAM (hybrid) |
Network router | 2-stage wormhole switched, XYZ routing, virtual channel flow control, 2 VCs per port, a buffer with depth of 5 flits per each VC, 8 flits per data packet, 1 flit per address packet, each flit is set to be 16-byte long |
Network topology | 3D network, each layer is a 4 × 4 mesh, each node in layer 1 has a router, 16 TSV links which are 128b bi-directional in each layer |
Pmax, Tmax | 110 W, 80°C |