Fig. 1
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
a A parallel MTJ. b An anti-parallel MTJ. c A STT-RAM cell
Fig. 1 | EURASIP Journal on Embedded Systems
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
a A parallel MTJ. b An anti-parallel MTJ. c A STT-RAM cell