Fig. 1
From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
a A parallel MTJ. b An anti-parallel MTJ. c A STT-RAM cell
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Fig. 1 | EURASIP Journal on Embedded Systems
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From: A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
a A parallel MTJ. b An anti-parallel MTJ. c A STT-RAM cell
