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Table 3 Separate execution times for four stages for DRH

From: Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

Data size No. of vectors Execution time in AXI_clk_cycles
Stage 1 S1→S2 reconfig. Stage 2 S2→S3 reconfig. Stage 3/iterations S3→S4 reconfig Stage 4 Total
24,448 382 50,879 68,103,418 887,481 68,121,324 351,467,386/361 68,112,480 1,718,389 558,461,357
48,960 765 101,761 68,097,812 1,760,340 68,108,008 235,622,553/242 68,109,251 3,436,924 445,236,649
73,408 1147 152,487 68,097,604 2,630,976 68,114,545 734,657,700/775 68,109,985 5,150,974 946,914,271
97,856 1529 203,239 68,098,307 3,501,560 68,120,760 180,065,909/185 68,108,534 6,865,011 394,963,320
122,368 1912 254,121 68,093,087 4,374,471 68,118,532 259,014,857/266 68,108,228 8,583,637 476,546,933
146,816 2294 304,821 68,097,653 5,245,029 68,117,134 343,858,083/353 68,112,569 10,297,674 564,032,963
171,264 2676 355,586 68,102,156 6,115,678 68,113,687 409,170,278/420 68,108,523 12,011,737 631,977,645
195,712 3058 406,299 68,102,063 6,986,275 68,119,069 215,183,290/221 68,110,364 13,725,761 440,633,121
220,224 3441 457,194 68,090,545 7,859,173 68,118,434 254,209,823/261 68,110,646 15,444,322 482,290,137
244,672 3823 508,843 68,074,050 8,730,693 68,095,324 789,451,907/810 68,088,858 17,159,321 1,020,108,996