Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

EURASIP Journal on Embedded Systems

Table 2 Separate execution times for four stages for SRH

Data size	No. of vectors	Execution time in AXI_clk_cycles
Data size	No. of vectors	Stage 1	Stage 2	Stage 3/iterations	Stage 4	Total
24,448	382	50,866	887,481	351,467,386/361	1,718,363	354,124,096
48,960	765	101,761	1,760,340	235,622,553/242	3,436,911	240,921,565
73,408	1147	152,487	2,630,976	755,125,927/775	5,150,948	763,060,338
97,856	1529	203,239	3,501,560	180,065,909/185	6,865,011	190,635,719
122,368	1912	254,095	4,374,471	259,014,857/266	8,583,585	272,227,008
146,816	2294	304,821	5,245,042	343,858,083/353	10,297,648	359,705,594
171,264	2676	355,586	6,115,652	409,170,278/420	12,011,737	427,653,253
195,712	3058	406,299	6,986,249	215,183,290/221	13,725,774	236,301,612
220,224	3441	457,194	7,859,173	254,209,810/261	5,444,335	277,970,512
244,672	3823	507,920	8,729,744	789,451,894/810	17,158,385	815,847,943