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EURASIP Journal on Embedded Systems

Table 1 Area-efficient microarchitecture sequence

From: A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

 

Address

Comparison

Cycle

0A

0B

1A

1B

2A

2B

3A

3B

0–1

0–2

0–3

0–4

0–5

0–6

0–7

1

0

1

2

3

4

5

6

7

0–1

0–2

0–3

0–4

0–5

0–6

0–7

2

0

8

9

     

0–8

0–9

     

3

1

2

3

4

5

6

7

8

1–2

1–3

1–4

1–5

1–6

1–7

1–8

4

1

9

      

1–9

      

5

2

3

4

5

6

7

8

9

2–3

2–4

2–5

2–6

2–7

2–8

2–9

6

3

4

5

6

7

8

9

 

3–4

3–5

3–6

3–7

3–8

3–9

 

7

4

5

6

7

8

9

  

4–5

4–6

4–7

4–8

4–9

  

8

5

6

7

8

9

   

5–6

5–7

5–8

5–9

   

9

6

7

8

9

    

6–7

6–8

6–9

    

10

7

8

9

     

7–8

7–9

     

11

8

9

      

8–9

      
  1. An exemplar of the sequencing of the dataflow through the area-efficient microarchitecture with extensibility factor m=4 and object count n=10. On each clock cycle, the microarchitecture requests the specified memory addresses from the memory groups and ports indicated. These data are subsequently compared according to the comparison sequence outlined
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