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EURASIP Journal on Embedded Systems

Table 6 Number of clock cycles and SQNR for 1D-DFT including data transfer times between the embedded engine and the host

From: Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine

   

Parameters

   

Reference

Implementation

Technology

(nm)

volt

(V)

Frequency

(MHz)

Max-point

DFT

Time to end

(μ s)

Power

(mW)

Normalized

power

Power

efficiency

SQNR

(dB)

[14]

Pipeline HW

350

1.5

25

1K

40.96

200

35.6

1.4

N/A

[25]

Configurable HW

180

1.8

86

8K

805

75.51

19.6

15.8

N/A

[18]

Configurable HW

180

1.8

200

8K

395

117

84.2

33

N/A

[5]

Configurable HW

65

1.3

866

4K

7.1

35

48.3

0.3

71.90

[26]

Configurable HW

180

1.8

150

8K

138

350

91

12.5

N/A

[19]

Configurable HW

180

1.8

70

2K

224

140

36.4

8.15

N/A

[2]

DSP

-

-

100

1K

403.3

N/A

N/A

N/A

N/A

[20]

ASIP

250

2.5

100

4K

52.80

275

26.6

1.4

61.23

[21]

ASIP

180

1.8

300

1K

13.8

N/A

N/A

N/A

N/A

     

1K

18.98

19

19

0.3

99.1

Proposed

ASIP

130

1.08

100

4K

42.2

25

25

1.05

97.84

     

8K

185.7

56

56

10.3

95.25

  1. [21]: Present the power consumption of functional unit and data address generator only
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