Skip to main content
EURASIP Journal on Embedded Systems

Table 3 Number of clock cycles and SQNR for 1D-DFT including data transfer times between the embedded engine and the host

From: Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine

N-point DFT

Cycles per

Latency @

100 MHz

SQNR

Scale factor

Scale factor

DFT

DFT

(dB)

(μ s)

s 1

s 2

s 3

s4

s 5

s 6

s 7

64

146

1.46

83.67

4

2

2

    

128

278

2.78

86.16

4

2

2

2

   

256

470

4.7

96.839

4

4

2

2

   

512

1002

10.02

96.37

4

4

2

2

2

  

1024

1898

18.98

99.1

4

4

2

2

2

  

2048

4222

42.22

98.97

4

4

2

2

2

2

 

4096

8318

83.18

97.84

4

4

4

2

2

2

 

8192

18578

185.78

95.25

4

4

4

2

2

2

2

Back to article page