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  • Research Article
  • Open Access

Word Length Selection Method for Controller Implementation on FPGAs Using the VHDL-2008 Fixed-Point and Floating-Point Packages

EURASIP Journal on Embedded Systems20102010:593264

https://doi.org/10.1155/2010/593264

  • Received: 23 December 2009
  • Accepted: 29 July 2010
  • Published:

Abstract

This paper presents a word length selection method for the implementation of digital controllers in both fixed-point and floating-point hardware on FPGAs. This method uses the new types defined in the VHDL-2008 fixed-point and floating-point packages. These packages allow customizing the word length of fixed and floating point representations and shorten the design cycle simplifying the design of arithmetic operations. The method performs bit-true simulations in order to determine the word length to represent the constant coefficients and the internal signals of the digital controller while maintaining the control system specifications. A mixed-signal simulation tool is used to simulate the closed loop system as a whole in order to analyze the impact of the quantization effects and loop delays on the control system performance. The method is applied to implement a digital controller for a switching power converter. The digital circuit is implemented on an FPGA, and the simulations are experimentally verified.

Keywords

  • Closed Loop System
  • Arithmetic Operation
  • Word Length
  • Loop System
  • Digital Circuit

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Authors’ Affiliations

(1)
Departamento de Ingeniería Electrónica y Comunicaciones, Universidad de Zaragoza, María de Luna 1, 50018 Zaragoza, Spain

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