Consider a processor organization consisting of a number of client modules and server modules (jointly called devices), like memory units and arithmetic-logic processing units. Suppose that these devices are interconnected with a bus which is segmented in such a way that devices connected to a particular segment can communicate in parallel to the data transfer operations going on in the other segments. This is achieved by a control logic which is able to reserve a continuous subsequence of the segments necessary to establish a path from the source to the target device. Given the frequency of data transfer operations between the devices, our task is to determine an efficient segmentation and segment-to-device assignment of this on-chip architecture. This task is formulated as an optimization problem which considers the amount of data transfer operations performed via the bus segments. The problem turns out to be NP hard but we propose efficient local search-based heuristics for it. The heuristics are applied to sample cases, and the outcome is an improved performance in terms of a shorter execution time.