Open Access

Improving the Performance of Bus Platforms by Means of Segmentation and Optimized Resource Allocation

EURASIP Journal on Embedded Systems20092009:867362

https://doi.org/10.1155/2009/867362

Received: 8 August 2008

Accepted: 5 April 2009

Published: 25 June 2009

Abstract

Consider a processor organization consisting of a number of client modules and server modules (jointly called devices), like memory units and arithmetic-logic processing units. Suppose that these devices are interconnected with a bus which is segmented in such a way that devices connected to a particular segment can communicate in parallel to the data transfer operations going on in the other segments. This is achieved by a control logic which is able to reserve a continuous subsequence of the segments necessary to establish a path from the source to the target device. Given the frequency of data transfer operations between the devices, our task is to determine an efficient segmentation and segment-to-device assignment of this on-chip architecture. This task is formulated as an optimization problem which considers the amount of data transfer operations performed via the bus segments. The problem turns out to be NP hard but we propose efficient local search-based heuristics for it. The heuristics are applied to sample cases, and the outcome is an improved performance in terms of a shorter execution time.

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Authors’ Affiliations

(1)
Automation Networks Department, ABB Corporate Research
(2)
Department of Information Technology, University of Turku and TUCS

Copyright

© T. Seceleanu et al. 2009

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.