Open Access

Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors

EURASIP Journal on Embedded Systems20092009:725438

https://doi.org/10.1155/2009/725438

Received: 25 March 2009

Accepted: 15 October 2009

Published: 6 December 2009

Abstract

Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathematical models have been proposed in the past. Most of these models are complex enough to be adapted for modern applications like run-time cache reconfiguration. This paper improves and validates previously proposed energy and throughput models for a data cache, which could be used for overhead analysis for various cache types with relatively small amount of inputs. These models analyze the energy and throughput of a data cache on an application basis, thus providing the hardware and software designer with the feedback vital to tune the cache or application for a given energy budget. The models are suitable for use at design time in the cache optimization process for embedded processors considering time and energy overhead or could be employed at runtime for reconfigurable architectures.

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Authors’ Affiliations

(1)
School of Computer Science and Electronic Engineering, University of Essex

Copyright

© M. Y. Qadri and K. D. McDonald-Maier 2009

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.