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EURASIP Journal on Embedded Systems
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A Formal Approach to the Verification of Networks on Chip

EURASIP Journal on Embedded Systems volume 2009, Article number: 548324 (2009) Cite this article

Abstract

The current technology allows the integration on a single die of complex systems-on-chip (SoCs) that are composed of manufactured blocks (IPs), interconnected through specialized networks on chip (NoCs). IPs have usually been validated by diverse techniques (simulation, test, formal verification) and the key problem remains the validation of the communication infrastructure. This paper addresses the formal verification of NoCs by means of a mechanized proof tool, the ACL2 theorem prover. A metamodel for NoCs has been developed and implemented in ACL2. This metamodel satisfies a generic correctness statement. Its verification for a particular NoC instance is reduced to discharging a set of proof obligations for each one of the NoC constituents. The methodology is demonstrated on a realistic and state-of-the-art design, the Spidergon network from STMicroelectronics.

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Authors and Affiliations

  1. Techniques of Informatics and Microelectronics for Integrated Systems Architecture (TIMA) Laboratory (CNRS, GrenobleINP, UJF), 46 Avenue Félix Viallet, 38031, Grenoble Cedex, France

    Dominique Borrione, Amr Helmy & Laurence Pierre

  2. Institute for Computing and Information Sciences (ICIS), Radboud University, Postbus 9010, 6500, GL Nijmegen, The Netherlands

    Julien Schmaltz

Authors
  1. Dominique Borrione
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  2. Amr Helmy
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  3. Laurence Pierre
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  4. Julien Schmaltz
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Corresponding author

Correspondence to Laurence Pierre.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Borrione, D., Helmy, A., Pierre, L. et al. A Formal Approach to the Verification of Networks on Chip. J Embedded Systems 2009, 548324 (2009). https://doi.org/10.1155/2009/548324

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  • DOI: https://doi.org/10.1155/2009/548324

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