A Formal Approach to the Verification of Networks on Chip

The current technology allows the integration on a single die of complex systems-on-chip (SoCs) that are composed of manufactured blocks (IPs), interconnected through specialized networks on chip (NoCs). IPs have usually been validated by diverse techniques (simulation, test, formal verification) and the key problem remains the validation of the communication infrastructure. This paper addresses the formal verification of NoCs by means of a mechanized proof tool, the ACL2 theorem prover. A metamodel for NoCs has been developed and implemented in ACL2. This metamodel satisfies a generic correctness statement. Its verification for a particular NoC instance is reduced to discharging a set of proof obligations for each one of the NoC constituents. The methodology is demonstrated on a realistic and state-of-the-art design, the Spidergon network from STMicroelectronics.

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Affiliations

1. Techniques of Informatics and Microelectronics for Integrated Systems Architecture (TIMA) Laboratory (CNRS, GrenobleINP, UJF), 46 Avenue Félix Viallet, 38031, Grenoble Cedex, France

   • Dominique Borrione
   • , Amr Helmy
   •  & Laurence Pierre

2. Institute for Computing and Information Sciences (ICIS), Radboud University, Postbus 9010, 6500, GL Nijmegen, The Netherlands

   • Julien Schmaltz

Corresponding author

Correspondence to Laurence Pierre.

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