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EURASIP Journal on Embedded Systems

Table 2 Example of conditions with reference to the system clock cycle. Queue 2 has been omitted because by the 14th clock cycle, it has not been used.

From: Efficient Processing of a Rainfall Simulation Watershed on an FPGA-Based Architecture with Fast Access to Neighbourhood Pixels

clk

in

Qx_sel

Loc

plat

inner

sv_x

Pixel status

we_tx

we_am

dir

min

Queue 1 contents

       

C

W

N

E

S

    

W

N

E

S

C

1

0

0

(0,0)

1

0

S

inv

inv

0

t4, t5

1

−3

—

—

—

2

2

Q1 = 4

(1,0)

1

0

N

inv

6

0

0

t5

1

−4

—

—

—

                    

3

2

Q1 = 5

(0,0)

1

0

S

6

inv

inv

0

0

—

0

—

—

—

—

—

                    

4

2

Q1 = 5

(1,0)

1

0

N

6

inv

6

0

0

—

0

—

—

—

—

—

                    

5

0

0

(0,1)

0

0

—

6

inv

0

0

—

1

−3

—

—

—

—

—

6

0

0

(0,2)

0

0

—

6

inv

0

0

—

1

1

—

—

—

—

—

7

0

0

(0,3)

0

0

—

6

inv

0

0

—

1

−4

—

—

—

—

—

8

0

0

(0,4)

1

1

E,S

0

6

inv

t3, t4

0

0

—

—

—

9

2

Q1 = 3

(0,5)

1

1

W,S

0

inv

0

t1, t4

0

0

—

—

                   

—

10

2

Q1 = 1

(0,4)

1

1

E,S

1

1

inv

1

1

—

0

0

0

—

—

                   

—

11

2

Q1 = 4

(1,4)

1

0

N,E,S

1

inv

1

t4, t5

1

−1

0

—

                   

—

                   

—

12

2

Q1 = 4

(1,5)

1

1

W,N,S

1

6

1

0

t4, t5

1

−1

0

—

                   

—

                   

—

                   

—

13

2

Q1 = 4

(2,4)

1

0

N,E,S

0

6

1

t4, t5

1

−1

—

                   

                   

—

                   

—

                   

—

14

2

Q1 = 4

(2,5)

1

1

W,N,S

1

6

1

0

t4

0

—

—

                   

                   

—

                   

—

                   

—

                   

—

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