EURASIP Journal on Embedded Systems

Table 3 Area results of the neural network-based FPGA face detector by different FPUs.

From: Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector

Bit-width	No. of Slices	No. of FFs	No. of LUTs
FPU32	1077	771	1952
FPU24	878 (–18.5%)	637	1577
FPU20	750 (–30.4%)	569	1356
FPU16	650 (–39.7%)	501	1167
FPU12	556 (–48.4%)	433	998

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