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  • Research Article
  • Open Access

An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing

  • 1Email author,
  • 1,
  • 1 and
  • 1
EURASIP Journal on Embedded Systems20092008:961315

https://doi.org/10.1155/2008/961315

  • Received: 1 March 2008
  • Accepted: 12 November 2008
  • Published:

Abstract

A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A pixel proof-of-concept chip was fabricated in a 0.35  m standard CMOS process, with a pixel size of 35  m 35  m. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.

Keywords

  • Parallel Architecture
  • CMOS Process
  • Image Processing System
  • Processor Array
  • Storage Capacitor

Publisher note

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Authors’ Affiliations

(1)
Laboratoire d'Electronique Informatique et Image (LE2I), UMR CNRS 5158, Health-STIC Federative Research Institute (IFR100), Burgundy University, 21078 Dijon, France

Copyright

© Dominique Ginhac et al. 2008

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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