An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing
EURASIP Journal on Embedded Systems volume 2008, Article number: 961315 (2009)
A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A pixel proof-of-concept chip was fabricated in a 0.35 m standard CMOS process, with a pixel size of 35 m 35 m. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.
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Ginhac, D., Dubois, J., Paindavoine, M. et al. An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing. J Embedded Systems 2008, 961315 (2009). https://doi.org/10.1155/2008/961315
- Parallel Architecture
- CMOS Process
- Image Processing System
- Processor Array
- Storage Capacitor