Compilation and Worst-Case Reaction Time Analysis for Multithreaded Esterel Processing
EURASIP Journal on Embedded Systems volume 2008, Article number: 594129 (2008)
The recently proposed reactive processing architectures are characterized by instruction set architectures (ISAs) that directly support reactive control fow including concurrency and preemption. These architectures provide efficient execution platforms for reactive synchronous programs; however, they do require novel compiler technologies, notably with respect to the handling of concurrency. Another key quality of the reactive architectures is that they have very predictable timing properties, which make it feasible to analyze their worst-case reaction time (WCRT). We present an approach to compile programs written in the synchronous language Esterel onto a reactive processing architecture that handles concurrency via priority-based multithreading. Building on this compilation approach, we also present a procedure for statically determining tight, safe upper bounds on the WCRT. Experimental results indicate the practicality of this approach, with WCRT estimates to be accurate within 22% on average.
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Boldt, M., Traulsen, C. & von Hanxleden, R. Compilation and Worst-Case Reaction Time Analysis for Multithreaded Esterel Processing. J Embedded Systems 2008, 594129 (2008). https://doi.org/10.1155/2008/594129
- Time Analysis
- Control Structure
- Reactive Control
- Timing Property
- Electronic Circuit