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  • Research Article
  • Open Access

Compilation and Worst-Case Reaction Time Analysis for Multithreaded Esterel Processing

EURASIP Journal on Embedded Systems20082008:594129

  • Received: 15 September 2007
  • Accepted: 18 April 2008
  • Published:


The recently proposed reactive processing architectures are characterized by instruction set architectures (ISAs) that directly support reactive control fow including concurrency and preemption. These architectures provide efficient execution platforms for reactive synchronous programs; however, they do require novel compiler technologies, notably with respect to the handling of concurrency. Another key quality of the reactive architectures is that they have very predictable timing properties, which make it feasible to analyze their worst-case reaction time (WCRT). We present an approach to compile programs written in the synchronous language Esterel onto a reactive processing architecture that handles concurrency via priority-based multithreading. Building on this compilation approach, we also present a procedure for statically determining tight, safe upper bounds on the WCRT. Experimental results indicate the practicality of this approach, with WCRT estimates to be accurate within 22% on average.


  • Time Analysis
  • Control Structure
  • Reactive Control
  • Timing Property
  • Electronic Circuit

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Authors’ Affiliations

Department of Computer Science, University of Kiel, 24118 Kiel, Germany


© Marian Boldt et al. 2008

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.